Analog to Digital convertor-Project

Discussion in 'The Projects Forum' started by ra1ph, May 6, 2011.

  1. ra1ph

    Thread Starter Active Member

    Jan 5, 2010
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    Hi,
    Wonder if someone can help me out.

    I have built the circuit below, but when the 7-seg displays the reading from the potentiometer the segments that are meant to be off are dim and the display is flickering.

    I wondering if the output of my ramp is the problem and is it possible to clean it up. I've attached the waveform. The project is built over 2 veroboards.

    I can supply more waveforms if necessary.
    Thanks in advance.

    [​IMG]

    [​IMG]
     
    Last edited: May 6, 2011
  2. bertus

    Administrator

    Apr 5, 2008
    15,645
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    Hello,

    What is the tollarance of the used resistors?
    You are not using buffers on the counters.
    See this page of the eBook for more info:
    The R/2R DAC

    Bertus
     
  3. ra1ph

    Thread Starter Active Member

    Jan 5, 2010
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    The tolerance of the resistors is 5%.

    Buffers? do not understand why I need them? this design was given to me by a lecturer. The counter outputs were to be connected to the EPROM. The feeds from the schmitt trigger to the Enable eprom Pin22 and the inverted feed to the 74HCT4543 Pin1 (latch disable) were to hold the 7-seg display steady.

    From reading through the ebook it seems that my design is a stairstep-ramp which "suffers from several limitations".

    Someone else has suggested to me that the 20KHz clock speed is the problem, would this be limiting factor of the design or maybe the veroboard.

    I was really hoping that you were going to tell me to put a filter on the ramp but I guess this will make no difference?

    Thanks for the reply!
     
  4. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    Can you get resistors with a lower tolerance like 1 %?
    This will improve the linearity a great deal.

    Bertus
     
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  5. ra1ph

    Thread Starter Active Member

    Jan 5, 2010
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    Not an option to get resistors now. Project and report to be handed in on Monday. I'll suggest using lower tolerance resistors in my report.

    Thanks for the help anyway!
     
  6. atferrari

    AAC Fanatic!

    Jan 6, 2004
    2,645
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    Maybe a Digital to Analog...?

    Your graphics are too small to see anything.
     
  7. Markd77

    Senior Member

    Sep 7, 2009
    2,803
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    If you've got a big pile of resistors you can try to match them. Either with a decent ohmeter or with a good voltage source and using the resistors in a voltage divider (keeping 1 resistor the same).
     
  8. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    This circuit ain't gonna work by Monday. It has serious "issues."

    U1 and U2 form a counter that supplies a crude R2R D2A converter. That stair step analog voltage is fed to comparator (-) U8 along with the voltage to be measured on the (+). When the stair step is greater then the measured voltage the comparator will go low, which looks like it (unnecessarily) enables the EPROM output and also latches the EPROM's output into the BCD to 7 segment displays. The EPROM is converting the 8 bit binary count value to BCD.

    *IF* everything is perfect then this thing might work. The first problem is any noise in either the stair step or the measured voltage will change where the thing actually triggers. That change means a different number will go to the 7 segments. And as this thing updates 2,500 times a second that will make the displays flash.

    You can prove the circuit is basically functioning by disconnecting U4-8 from the R2R and connecting to say U3-34(? QA) which should show a constant 17 on the display when the pot is close to mid value.

    It is left as an exercise for the student to determine where "17" comes from.


    When matching 5% resistors remember there will be NO resistors at the nominal value. These were sorted out and sold (for more money) at their better tolerance value.
     
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  9. ra1ph

    Thread Starter Active Member

    Jan 5, 2010
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    Thanks for this. This is the type of information I was looking for. Basically the design is flawed.
    You are right about "unnecessary enable EPROM output"
    I have reduced the clock frequency to 1 Khz with a frequency divided and there is no flickering on 7-Seg (U7) and reduced flickering on U5.

    Could you tell us a bit more on the steady "17" you suggested? couldn't follow your instructions (I know the image is bad) I posted a better one

    Thanks
    [​IMG]
     
  10. ErnieM

    AAC Fanatic!

    Apr 24, 2011
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    Of course the design is flawed. *EVERY* design is flawed. No exceptions.

    Just sometimes you can get by with some things in some situations. I can see a few useful applications: since this is a class exercise you may just learn more from trying to fix something marginal then seeing something flawless. The school of hard knocks makes the best lessons. A micro controller would do this function neatly in one IC, but it is a good lesson to see this function built discretely (what we used to call "random logic" as yiou randomly pick standard logic function ICs) to learn these blocks: you will need to know some useful blocks if you ever do FPGA designs.

    Also, since your instructor probably designed it remember it is THE BEST CIRCUIT EVAR. Say that at least once in response to a question in class. Mumble it under your breath a few times when teacher is within earshot.

    Very good. The lower digit will tend to have more flicker as it is more sensitive to noise, it has more resolution.

    About the "17:" 17 is the state where U3-QA on pin 14 first goes high. By connecting this digital signal to the comparator instead of the stair step you get the comparator to trip at the digital number that makes that line go high.

    I'm going to retreat from saying this give you a constant "17" as I don't see anything to prevent additional clocking into the display drivers U4 & U6. So that makes flicker. My bad.

    The latching may be there and I am missing it. What I do see is the 4534's are level loaded latches, they load for the pin LD=1 and hold for LD=0, and looks like the comparator that makes LD low when the stair step just goes higher then the pot. It could be that is why the EPROM output is disabled until an analog match is made.

    So slowing things down makes it better. See what you can do about the signals around the comparator, some small cap (0.01uF is probably BIG) that kills noise but lets signal change should help.

    You can put more cap on the pot center tap then the stair step, as the step needs to change once a clock but the pot is constant until you turn it.
     
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  11. ra1ph

    Thread Starter Active Member

    Jan 5, 2010
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    I just notice that I had left out the latching part in the drawing I posted. This is the actual way the board is wired
    [​IMG]
    and here is the waveform on Pin 6 of the inverter.
    [​IMG]


    Put cap on the center tap of the pot didn't have anything small enough to put at the comparator. Still have the flickering 7-segment display though this is a problem with my ramp.

    Thanks again for you time and replies. It's will be handed in tomorrow by someone who has a lot more knowledge than the person who first started the project
     
    Last edited: May 8, 2011
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