Hi, I am asked to design an OpAmp suitable for a filter of a specified frequency with a two-phase clock. Hence, the step response of the filter must be such that it settles to an adequate level within about 40% of the total clock period. I have not properly understood the above mentioned specification. What more has to be done to meet the specification? How do I start with the design? I have the idea to design a basic opamp, ie to decide the width and length of PMOS and NMOS in a diff pair n current mirror and to design the basic bias circuitry. Also, it will be helpful if you can me some links to read about OpAmp design. cheers.