Dear all,

We have been assigned a bonus project that upon completion will reward us with an extra 20% on our grade! (yes crazy, but its definitely out of our league)

This is what the assignment handout reads:
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1.1 DESIGN REQUIREMENTS
Design an amplifier with a minimum gain of 10 @ 10 KHz, minimum voltage swing of 5 volts (p-p) at the output, maximum output resistance of 1 kΩ, and minimum input resistance of 50 kΩ. You may use up to 2 transistors (e.g two 2N7000 MOSFETs or two PN2222 BJTs, or one MOSFET and one BJT). Make sure that you only use standard resistors. Use only one power supply with a voltage of 12 volts. Make sure the distortion is minimized (i.e. bias the transistors away from cut-off or triode/saturation). It is ok to have a design better than the specifications (e.g. gain > 10, or Rout < 1 kΩ). Simulate your circuit on Multisim BEFORE the lab session.

1.2 LAB WORK
a) Assemble your design in the lab. Measure and record the DC values of the voltages for all the nodes of your circuit. Estimate the currents.

b) Choose Vsig to be 250*sin(20000π t) mV (i.e. 500 mV p-to-p). Measure the AC output voltage. Plot the input and output signals on the same screen. What is the voltage gain Vo/Vsig? Compare it with your theoretical calculation.

c) Measure the input resistance by measuring the AC voltage of the base/gate and the input voltage Vsig. Compare it with your theoretical calculation.

d) Measure the output resistance by measuring the gain, once for a load resistor of 1 kΩ and once by measuring the gain without the load resistor. Estimate the output resistance based on the two measurements. Compare it with your theoretical calculation.

1.3 RESULTS
1) Measurements:
Measure the DC and AC voltages of all the nodes of the circuit. Measure the voltage gain Vo/Vsig, input resistance, and output resistance and compare them with your theoretical calculations.

2) Simulation:
Simulate your circuit on Multisim. Include the plots of input and output voltages in your report.

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Just finished making a 1L coffee jug. I have been preparing for the past 2 hours on transistors (BJT and MOSFET's) and I still feel that I do not understand circuit examples that are presented. However, the most helpful and simplified reading I got my hands on was the following:

http://people.seas.harvard.edu/~jones/es154/lectures/lecture_3/bjt_amps/bjt_amps.htmlhttp://people.seas.harvard.edu/~jones/es154/lectures/lecture_3/bjt_amps/bjt_amps.html

Correct me if I'm wrong but I think using 2 BJT's in the Common Emitter configuration would be the way to go on this.

Anyhow, How should I start tackling this problem?

Your input is greatly appreciated.

 

Why 4 hours?

 

Because I feel like pulling an all-nighter on this stuff although its due at the end of this week. Interesting stuff

Ok, I read some more and it seems like I need use a Common-Emitter gain stage (to satisfy the high voltage gain, and the output resistance of 1kΩ),

followed by an Emitter-Follower (to satisfy the high input resistance of 50kΩ).

I will start my calculations and update on here every 20 mins.

My strategy of attacking this is first building the Common-Emitter separately and checking if it meets the first 2 requirements, then working on the Emitter-Follower.

 

Yes keep us posted I would be interested in seeing how you make out with this, design.

 

Ok, the first equation I used was input resistance,

1. r∏ = (β+1) Re;

I looked up the value of beta for a PN2222 BJT, and sources say its 100.
R∏ = 50kΩ

Therefore, Re = 495Ω.

Now moving the Voltage Gain equation,

2. Vo/Vi = [ β(Rc || Ro) ] / (Rs + r∏).

Ro = 1kΩ (from given requirements)

I am stuck here. I have the value of Re, β and Ro but what about Rc and Rs?

 

Are you using 50K ohms for the emitter resistor?

Start with this. since you cannot saturate or put the transistor close to cutoff, then they are asking for a linear amplifier.

So that means make voltage at the collector (VC) = 1/2 supply voltage. (VCC)

 

From your above statement I sense that I've made an error in my first calculation

In the first equation: the Input resistance, r∏ = (β+1) Re. Hence, Re would be:

50kΩ/ (101) = 495Ω.

But I would still be stuck in the second equation since I dont have Rc or Rs

 

β = 200 for a PN2222 BJT, so my modified calculations would be:

Ok, the first equation I used was input resistance,

1. r∏ = (β+1) Re;

I looked up the value of beta for a PN2222 BJT, and sources say its 200.
R∏ = 50kΩ

Therefore, Re = 250Ω.

Now moving the Voltage Gain equation,

2. Vo/Vi = [ β(Rc || Ro) ] / (Rs + r∏).

Ro = 1kΩ (from given requirements)

I am stuck here. I have the value of Re, β and Ro but what about Rc and Rs?

 

My Vcc here would be 5Volts right?

 

My Vcc here would be 5Volts right?

If you mean your voltage at the collector around 6V. used for calculations.

VCC is the supply voltage of 12V.

Also remember voltage gain (Av.) is calculated as (Rc / RE)

If you include a load then Av. is = to (RC // Rload, divided by, RE)

Keep working at it you'll get it.

 

My Rc should be infinity, correct? since in the table provided in my first post. It says that the output resistance is equal to (Rc || Ro). If Rc was to be infinity then the output resistance is equal to Ro.

 

My Rc should be infinity, correct? since in the table provided in my first post. It says that the output resistance is equal to (Rc || Ro). If Rc was to be infinity then the output resistance is equal to Ro.

Alright,

Rc is needed to develope a voltage across your capacitive coupled load.

Now if your load is 1K ohms, then for starters use a 1K ohm resistor for RC.

Calculate the current through this resistor, using (1/2 VCC / RC)
That gives you collector current (IC).


Now also if you are using a CC stage , this has NO voltage gain, so all the gain must come from your CE stage.

It woulod be more advisable to use 2 CE stages and split the gain.

 

I will give you a basic beginers course in biasing a transistor CE stage.

Then you can take it from there. OK.

 

Using a NPN transistor.

1. Use a resistor value for RC = to Rload.

2. Calculate collector current {(0.5 x VCC) / RC } = IC

3. Choose a voltage gain (Av.) value between 1 and 20.

4. Calculate RE by ( RC // Rload ,divided by, Av.) = RE

5. calculate emitter voltage (VE) by (IC x RE) = VE

6. calc. base voltage (VB) by (VE + Vbe) = VB

7. choose a value for base to ground voltage divider resistor by (RE x 10) = RB1

8. calc. divider current by ( VB / RB1 ) = ID.

9. calc. base to supply voltage divider resistor by {( VCC - VB ) / ID.} = RB2

10.Run a simulation or build it. (PROTOTYPE IT)

And check for VC to be around (1/2 VCC)

check VB make sure it is close to calc. values.

and VE to make sure it is close.

Then do a dynamic AC signal test:

Then check for waveforms distortion, and signal gain.

 

Ok, I got totally confused. I am starting everything from scratch again.

The transistor type is PN2222 and not the 2N2222.

Question #1: How do I find the internal emitter resistance from a data sheet?

Question #2: Having found the internal emitter resistance (re), the formula for the input resistance of a Common-Emitter transistor is:

Rin = Rb || (beta + 1) re.

and beta is 100 for a PN2222.

Hence, Rin = Rb || (101) re

Now how on earth would I achieve a minimum input resistance of 50k ohms with the above fomula?

After some thinking, I've looked at the Common-Emitter with Emitter Resistance of which the input resistance formula is:

Rin = Rb || (101) (re + Re),

So I thought maybe I can use a value for Re high enough to achieve the 50k, but then looking at the voltage gain formula, the Re would be hindering it!

Any input?

Just read your post, give me some time to digest. Thanks

 

Yes ,you are getting very close to figuring this out, what your initial way of doing this was to use the inherent input impedance of the transistor itself, which runs into a lot of problems, that's why a designer will design the stage with external resistors, as to bias it so that the changing parameters of the transistor component does not have as much affect on the outcome.

You have learned this very quickly, realizing voltage gain and high input impedances and low output imp. all that stuff aint mixing right.

I simulated it using 2 common emitter stages, (pn2222) and got the 2.6V peek.out, with a 250 mV. pk. in.
Also breadboarded it with (2N3904) and got the same results.

But it took some odd impedance matching, from input to output, because of the high input impedance needed, and a low output impedance asked for.

First learn how to bias the transistor into the linear region. as my #14 post showed.

Then from there we can look at what needs to be done to get the impedances and gains specified.

 

1. Use a resistor value for RC = to Rload.

Ok, I used Rc = RL = 1kΩ.

2. Calculate collector current {(0.5 x VCC) / RC } = IC

Ic = (Vcc/2)/Rc = 6 / 1kΩ = 6mA.

3. Choose a voltage gain (Av.) value between 1 and 20.

Av = 10. (as per requirement)

4. Calculate RE by ( RC // Rload ,divided by, Av.) = RE

Re = (Rc || RL) / Av. => (1000 || 1000) / 10 => 500/10 = 50Ω.

5. calculate emitter voltage (VE) by (IC x RE) = VE

Ve = Ic x Re = 6mA x 50 = 0.3V.

6. calc. base voltage (VB) by (VE + Vbe) = VB

Vb = Ve + Vbe = 0.3 + Vbe (How do you find out Vbe?)

7. choose a value for base to ground voltage divider resistor by (RE x 10) = RB1

Rb1 = Re x 10 = 50 x 10 = 500Ω.

*(Which Rb are you talking about?, I'm looking at the Sedra/Smith Textbook, Fifth Edition, page. 484 on the circuit of CE with Emitter Resistance)

8. calc. divider current by ( VB / RB1 ) = ID.

Id = (0.3 + Vbe)/ 500.

*(I dont understand what is Id?)

9. calc. base to supply voltage divider resistor by {( VCC - VB ) / ID.} = RB2

Rb2 = (12 - (0.3 + Vbe))/ Id.

10.Run a simulation or build it. (PROTOTYPE IT)

I am not able to simulate it right now since the labs are closed. However, they open in approximately 3 hours.

 

The classic voltage divider base bias.

ID is the current through the resistor voltage divider network.

 

Here is what you have so far.

Draw this up on a sheet of paper.

And solve for RB2.

 

Then once you get that drawn up we will change some values to get a higher input impedance.