Altium designer and multichannel Schematic??

Discussion in 'Electronics Resources' started by alexglvr, May 11, 2010.

  1. alexglvr

    Thread Starter New Member

    May 11, 2010

    In a the schlib of my altium project, I defined a Xilinx FPGA as a multi-part component (PARTA : Bank0, PARTB : Bank1, PARTC : Bank2, PARTD : Bank3, PARTE : Supply).

    I then defined one schematic per part
    (Bank1.sch deals with the FPGA bank1 wiring and environemnt,
    Bank2.sch deals with the FPGA bank2 wiring and environemnt, etc...)
    and one for the power supply (supply.sch)

    A upper level schematic (FPGA.sch) implements Bank1.sch, Bank2.sch, ..., Supply.sch.

    On the top level schematic, Implements FPGA.sch

    It then gives the following hierarchy:


    If my TOP design (TOP.sch) implements 1 FPGA structure (one sheet symbol pointing to FPGA.sch), it works well. My generated PCB has a single FPGA.

    BUT, If my TOP design uses several FPGA structures, then the sub-circuit seems not to be recognised and i have a footprint per FPGA sub-circuit on the generated PCB (ie 5 FPGA per FPGA.sch instance)

    And yet, the sheet symbols used on the TOP schematic to instanciate FPGA.sch do not have the same designator, neither the same Unique ID...

    It looks like if altium was not keeping the hierachy after the FPGA.sch level. It then deals with several FPGA components part, but do not manage to merge them correctly to create the full component...

    Do you have any idea on how to solve that?

    Thank you,

  2. svenn

    New Member

    Jul 2, 2010
    What is supply.sch doing inside the fpga.sch? Are you laying out the internal power distribution of the FPGA?

    Other programs solve this by using designators like U1-a U1-b U1-c on the different multipart symbols, where U1 is the FPGA that you instantiate in your schematic and -a -b etc. are part symbols with pins.

    To me it looks as if you have created a hierarchical schematic where you are actually looking for a multi-page schematic since supply.sch is inside FPGA.sch. But I also know that Altium boost some kind of easy FPGA design in their newer tools and evaluation boards, where the developer has tight control over the FPGA.

    What are you trying to do? Design the logic which will be inside the FPGA by schematic capture? Design the PCB where the FPGA will be mounted? Both?