Altera Quartus Problem

Discussion in 'The Projects Forum' started by MrL, Feb 19, 2012.

  1. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    Hi,

    I'm working on simulating my project within Altera Quartus 11. I'm using VHDL code to simulate the design.

    I'm giving a signal assignment to one of the inputs, but my test output on the same channel gives a different value to the one that has been assigned. The circuit and waveform are shown below:

    http://img26.imageshack.us/img26/8428/circuits.png
    http://imageshack.us/photo/my-images/818/waveform.png/

    The two signals i'm referring to are mux_vcc (input) and mux_test (output), which are both connected to the same channel, and can be seen in the schematic. Although in my VHDL code i'm assigning mux_vcc (input) as 0, mux_test (output) is 1 at the very start of the simulation.

    I was wondering if someone would please be able to help me out, as one of the purposes of my circuit is to detect the first 1 bit, and this issue means i'm unable to confirm it's performance.

    Below is my signal assignments used in VHDL:
    Code ( (Unknown Language)):
    1. mux_vcc <=  '0',
    2.         '1' after 300 ns;
    3. data_in <=  '0',
    4.         '1' after 1.142 us,
    5.         '0' after 1.213 us,
    6.         '1' after 1.283 us,
    7.         '1' after 1.354 us,
    8.         '0' after 1.425 us,
    9.         '0' after 1.496 us,
    10.         '1' after 1.567 us,
    11.         '0' after 1.638 us,
    12.         '1' after 1.709 us,
    13.         '1' after 1.780 us,
    14.         '0' after 1.850 us,
    15.         '1' after 1.921 us;  
    16. for i in 1 to num_clk_cycles loop
    17.     tran_clock <= not tran_clock;
    18.     wait for clk_period/2;
    19.     tran_clock <= not tran_clock;
    20.     wait for clk_period/2;
    Any help would be greatly appreciated.

    Thanks.
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    I don't see the assignment for mux_test in your code. Please show where that signal gets assigned to mux_vcc.

    PS: Never mind, I see the problem is updating mux_vcc. Give me a second.

    On third thought, I'm going to need to see the assignment to mux_test.
     
  3. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    Thanks for the reply.

    I haven't assigned a value to mux_test. I have assigned a value to mux_vcc, which is the input, but with the mux_test output being connected to the same node, i was assuming that it would take up the same value as the mux_vcc input.
     
  4. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    How is mux_test connected to the same node without an assugnment? In VHDL, connections are made via assignments.

    Are you using graphics design entry?
     
  5. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    I gotta run. I'll just leave you with this comment. In simulations, connections are made via assignments. If you're using a graphical entry method, then the underlying code is probably being automatically generated. Now, updating signals in assignments depend on a changed in the incoming signal. It appears that mux_test is updating on the next clock after a change of mux_vcc. In that case, the underlying code is using the clock signal to update mux_test. Try changing the clock period to verify.

    Note: This is an edit from the first version of my post. Sorry for any confusion that might have caused.
     
  6. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    Thanks for the help. I'll have a little play around and let you know how i get on.
     
  7. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    What i've is this delay is not dependent on the clock, and is in fact a fixed delay of roughly 6.5ns. When assigning a signal value, the delay occurs when updating this value on the channel/node. Would a functional simulation rather than a timing simulation overcome this?
     
  8. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    That was a good test. I'd say the dealy is being modeled in your simulation. If so, I don't know a way to get rid of it, except for finding the generated code and modifying it. Otherwise, there might be some options in your graphical entry program ( wich I have to assume you're using one, since you didn't answer my question about that ) options that allow you to set zero delays or else set the value you want. You'll have to read the documentation for that particular package, however.
     
  9. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    PS another thought comes to mind. You mentioned functional vs timing simulation. Are you running a timing sim? Are you using back-annotated gate delays in your simulation? If you're doing someting as extravagant as all that, then yes, running a simple functional simulation might help.
     
  10. MrL

    Thread Starter Member

    Oct 21, 2009
    46
    0
    For the simulation, i am using Altera Quartus to build the design, and then simulating this in Modelsim Altera. As i'm pretty inexperienced with this type of stuff, i'm assuming this would come under graphical simulation?

    I'm running a gate level simulation in Altera Quartus, so i'll try and figure out how to run a functional simulation. Thanks for the help.
     
  11. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    For a functional simulation, you don't build the design at all, but rather just use the native code files. I can't help doing a simulation on a graphical entry, as all my work is in VHDL/Verilog. Anyway, you just load your design straight into the tool, don't build it.
     
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