Allaboutcircuits CMOS Gate Circuitry Example Truth Table

Discussion in 'Homework Help' started by Bangersandmash, Aug 24, 2016.

  1. Bangersandmash

    Thread Starter New Member

    Jun 10, 2016
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    Hi everyone this is not homework but I'd appreciate some help,

    I am looking through the notes on the following link http://www.allaboutcircuits.com/textbook/digital/chpt-3/cmos-gate-circuitry/.

    Does anybody have a truth table for the CMOS AND gate circuit with the inverter (Image attached) so i can see how the inverter behaves?

    I am looking to see how Q5, Q6 would function and the output from each state.

    Thanks
     
  2. WBahn

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    Mar 31, 2012
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    The inverter behaves like an inverter. Whatever the logic level its input voltage is compliant with, the output is compliant with the opposite level.
     
  3. Bangersandmash

    Thread Starter New Member

    Jun 10, 2016
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    So how does Q5 and Q6 respond to the input?

    Would Q5 and Q6 be on or off?

    What would the truth table look like?
    A B Q1 Q2 Q3 Q4 Q5 Q6 Output
    0 0 On On Off Off
    0 1 Off On On Off
    1 0 On Off Off On
    1 1 Off Off On On
     
  4. WBahn

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    Mar 31, 2012
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    Add a column between Q4 and Q5 and enter the logic levels of the node that connects the output of the NAND gate to the input of the NOT gate (i.e., the node that connected to the gates of Q4 and Q5).
     
  5. Bangersandmash

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    Jun 10, 2016
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    AB Q1 Q2 Q3 Q4 Value Q5 Q6 Output
    0 0 On On Off Off 1
    0 1 Off On On Off 1
    1 0 On Off Off On 1
    1 1 Off Off On On 0
     
  6. WBahn

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    Mar 31, 2012
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    Okay, so now do the same thing you did for Q1 through Q4. You know the logic level of the gates of Q5 and Q6. So which ones are On and which ones are Off.
     
  7. Bangersandmash

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    Jun 10, 2016
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    AB Q1 Q2 Q3 Q4 Value Q5 Q6 Output
    0 0 On On Off Off 1 Off On 0
    0 1 Off On On Off 1 Off On 0
    1 0 On Off Off On 1 Off On 0
    1 1 Off Off On On 0 On Off 1
     
  8. WBahn

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    Mar 31, 2012
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    Very good. And you did it on your own.

    Does it answer your original concerns?
     
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  9. Bangersandmash

    Thread Starter New Member

    Jun 10, 2016
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    Thanks for the pointers
     
  10. Bangersandmash

    Thread Starter New Member

    Jun 10, 2016
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    So is this CMOS gate classed as a NAND gate or an AND gate?
     
  11. MrChips

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    Oct 2, 2009
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    It is a 2-input NAND gate.
    It is also a 2-input AND gate with negative logic output.
    It is also a 2-input OR gate with negative logic inputs.
     
  12. Bangersandmash

    Thread Starter New Member

    Jun 10, 2016
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    Are the lesson notes wrong then. The circuit is labelled as a CMOS AND gate.
     
  13. WBahn

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    Mar 31, 2012
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    Look at your truth table! The final output is a 1 only if (A is True) AND (B is True). So what function does it implement?

    The left-hand side is a NAND gate (which is short for NOT AND) and the right hand side is a NOT gate.

    So we have a NOT (NOT AND) gate. The two NOT gates functionally cancel out leaving us with just and AND gate.
     
  14. WBahn

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    Mar 31, 2012
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    Are you talking about the entire gate circuit, or just the first stage?

    Assuming you are talking about just the first stage (the NAND portion), then another one worth mentioning is:
    It is also a 2-input NOR gate eith negative logic input and output.
     
  15. MrChips

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    Oct 2, 2009
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    Sorry, I didn't look at any schematic. I assume from the discussion of the posts that you were discussing a NAND gate. Now I will go back to look.

    So if we are seeing an AND gate.

    A 2-input AND gate is also a 2-input OR gate with negative logic inputs and negative logic output.
     
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