1. Blackson

    Thread Starter New Member

    Dec 28, 2012
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    I am having trouble understanding the timing diagrams. The data sheet says that data is ready after "access time" from the rising edge of the read clock. But when is that? The diagrams suggest it is late in the cycle. The data sheet says that the "maximum" (at 3.3v) is 15ns. So I am confused. I would also like to understand the setup times for read reset and read enable. The data sheet specifies a "minimum," but the diagrams suggests that these times are longer. Help is appreciated.
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    First of all, I would stay away from a chip that has such crappy datasheet. I think I understand what you mean, I think the two different lines on the rising edge of clock represent the decision levels for low-to-high and vice versa transitions as described in table 7.2, but who the hell is supposed to guess that..
     
  3. Blackson

    Thread Starter New Member

    Dec 28, 2012
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    Thanks for looking at it. And thanks for letting me know that it is poorly written. I am new at this stuff. I agree that that the two lines represent transitions. But when am I supposed to read the data? This is my main question. The sheet says that data is available after "access time," but I don't know when that is. Is it possible to tell from the diagrams? I would just abandon the chip, but I am into it now. Also, the chip is used in the CMUcam, so I assume it can't be that bad.
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    As I see it, data is stable 15ns after the "top part" of rising edge of RCK. I have no idea if the company is still living, but you may need to ask them about what they actually meant to say in the datasheet. Personally I hate when I have to use parts that have datasheets, but you can´t really tell if what they show is just a mere coincidence, or they put multiple processes in the same diagram, or it absolutely has to be in that particular order.
     
  5. Blackson

    Thread Starter New Member

    Dec 28, 2012
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    That seems right, according to the table. But why do the diagrams show the nth data so late in the nth cycle? The data looks like it is ready after the low and into the high of the next cycle. Also, in these diagrams, Tac (access time) looks to extend way into the cycle. What is the data sheet trying to convey in these diagrams?
     
  6. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    15ns is not a very long time, imagne you clock it at 1/10th of the clock in the diagram, suddenly the timing looks pretty reasonable. You simply need to make your circuit that receives the data work in such way that it is sure that it reads the data in the time period when it is valid. For a set clock rate you might use the falling edge of the clockfro example, if it gets you there more easily.
     
  7. Blackson

    Thread Starter New Member

    Dec 28, 2012
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    Your suggestion that the diagram has a clock rate was helpful to me. I never thought of that. Maybe the diagram is running at the fastest clock. Is there a convention about the clock in a diagram? If it is the fastest clock, it sort of makes sense of the length of Tac. According to the table, the minimum RCK cycle is 20ns. But how is this number consistent with the other numbers in the table. The minimum high and low pulses are 7ns respectively, and the minimum transition is 2ns. But doesn't that add up to 18ns? (By the way, I tried reading the data at the low of the cycle but got garbage. Maybe the problem is in my code, so I wanted to make sure I understood the timing diagrams, which has not been easy.)
     
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