Hello, everybody I designed CMOS and CPL full adders but they don't work.. both CMOS and CPL XOR gates work correctly but when I put them into the adder circuits, the results don't make any sense. Is there anyone has idea what is the problem? At first, I thought it was a problem with CPL transistors, cause this was my first time to design CPL logics. But CMOS adder also doesn't work correctly, so I think it's not a problem with CPL. Then, I thought it was a MOS sizing problem so I tried to fix it, but I have no idea which one I have to change. Please let me know what's the problem and possible way to fix. I'm working in Cadence Virtuoso. Thanks.