Adder/Subtractor with Error Detector

Discussion in 'The Projects Forum' started by uptomike, Dec 15, 2012.

  1. uptomike

    Thread Starter New Member

    Dec 13, 2012
    I'm "building" a fou-bit adder/subtractor using Quartus II. When I connect to the trainer board, everything works fine - adds, subtracts, +/- sign, correct decimal readout...problem is, the instructor wants an error detector to indicate an incorrect result (e.g. when you add 2 to 6, readout is "-8"; we want "E -8"). Our big hint was to use the adder overflow. But I can't get it to work correctly. The error shows in the adder, before it is clocked. When I try to add 6+2, it shows up as E06.

    I have the lpm adder/subtractor going into a DFF, which then goes through a parser and then to the 7 segment display. One output of the parser goes to the second (sign) 7 segment for +/- (set up to read either "0" for positive, "-" for negative).

    The overflow has been set up to:
    1 - go directly to the 7 segment to read "E" when there's an error.
    2 - go through an AND gate to delay it until it is clocked.
    3 - go through a latch to delay it.

    None of these schemes has worked. Seven (smart) students are stuck on this, our last project. Any ideas?
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
  3. uptomike

    Thread Starter New Member

    Dec 13, 2012
    That solution looks good to build on a breadboard, but the problem I have is that the circuit is designed using the Quartus software and sent to a FPGA. The adder/subtractor is a pre-designed component; I have no access to the interior. That means I can't connect to the bits between the adder components. Everything has to connect externally to the adder.

    Do you have any other suggestions?
  4. tshuck

    Well-Known Member

    Oct 18, 2012