Adc

Discussion in 'Programmer's Corner' started by tosameena, Dec 4, 2007.

  1. tosameena

    Thread Starter New Member

    Aug 22, 2007
    8
    0
    hi all,

    i have written a code for ADC in VHDL..
    the problem is with the type syntax..

    Type state(s0,s1,s2,s3,s4,s5,s6,s7) is std_logic_vector (3 downto 0);
    type state is array(3 downto 0) of std_logic_vector;

    im getting error stating that s0 to s7 is not declared....

    can you please help me out in correcting it...

    thank you
     
  2. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
    145
    To start with have you put:

    Code ( (Unknown Language)):
    1. library ieee;
    2. use ieee.std_logic_1164.all;
    At the start of the code?

    Dave
     
  3. tosameena

    Thread Starter New Member

    Aug 22, 2007
    8
    0
    yes..
    i have included the library....
     
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