ADC: kSPS

Discussion in 'General Electronics Chat' started by Management, Nov 23, 2009.

  1. Management

    Thread Starter Active Member

    Sep 18, 2007
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    I know what drives the N-bit choice of a ADC/DAC but what drives the samples per second spec on an Analog to Digital Converter?

    Thinking about using a AD7680. It's a 16-bit 100 kSPS ADC. An input range of zero to about 5.5 volts and the highest frequency of 2200 Hz.
     
    Last edited: Nov 25, 2009
  2. t06afre

    AAC Fanatic!

    May 11, 2009
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    It is the SCLK input the drives the conversion. 1 conversion takes 20 SCLK cycles. You can use 2.5 MHz as max SCLK frequency and 250KHz as min frequency.
     
  3. Management

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    Sep 18, 2007
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    Did you take this from the datasheet?

    Thanks for the reply.
     
  4. t06afre

    AAC Fanatic!

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    Yes it is all in the data sheet;)
     
  5. Management

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    Sep 18, 2007
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    What if the CLK speed is much higher?
     
  6. t06afre

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    The clock speed, is specified by the manufacturer. So going outside these limits will produce erratic errors. I can not give you a more precise answer than that
     
  7. Ron H

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    Apr 14, 2005
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    According to the datasheet, SCLK minimum is 10kHz.
     
  8. t06afre

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    Not as I read it. But anyway the OP wanted the fast samplerate so it does not matter.
     
  9. blueroomelectronics

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    Jul 22, 2007
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    What are you trying to sample?
     
  10. Ron H

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    Turns out I was looking at a preliminary datasheet from datasheetcatalog.org.
     
  11. Management

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    Sep 18, 2007
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    A 4-20 mA with HART Comm (1 mA peak to peak) riding on top of it at a maximum frequency of 2200 Hz running through a 250 Ohm sense resistor.
     
  12. kubeek

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    Sep 20, 2005
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    2200Hz or 2200MHz? thats a huge difference
     
  13. Management

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    Sep 18, 2007
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    Sorry about that. It's suppose to read 2200 Hz.
     
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