active or asserted input state in logic gates

Discussion in 'General Electronics Chat' started by PG1995, Oct 16, 2011.

  1. PG1995

    Thread Starter Active Member

    Apr 15, 2011
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    Hi

    Please have look on the attachment. Please help me with that para. The author uses the same terminology at other places. Thanks for the help.
     
  2. praondevou

    AAC Fanatic!

    Jul 9, 2011
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    You won't see an inverter symbol with a bubble on the input so much (as a single symbol). What you will see are more complex IC symbols where there is a bubble on the input. Usually "Active Low" means just that this input will normally be "High" and to fulfill it's function it will have to be asserted or pulled to "Low".

    [​IMG]
    example: you see the bubble on pin 4? That means to reset the 555 you will need to pull this pin to LOW. If it's connected to Vcc it's just doing nothing.

    Here you have some other examples of active-low inputs.
     
  3. PG1995

    Thread Starter Active Member

    Apr 15, 2011
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    Thanks a lot, praondevou. But I'm sorry I still don't exactly understand it. Could you please help me a little more?

    "HIGH" and "LOW" simply mean logic state "1" and "0" respectively. What do "asserted" and "pulled" mean in this context?

    ""Active Low" means just that this input will normally be "High"" :- See, here's the confusion. In my opinion, input will neither be HIGH nor LOW. We set it to be either HIGH or LOW by supplying it with the specified voltage which could either be 5V or 0V. For example, in the IC 74LS04 below, I would define it if input pin #3 is HIGH or LOW by supplying it with the specified voltage.

    [​IMG]


    What do you mean by "reset"? Please let me know.

    Okay. If it's connected to GND then what would it be doing then? Please let me know.

    Thank you very much for all the help and your time.

    Regards
    PG
     
  4. SgtWookie

    Expert

    Jul 17, 2007
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    If you look at the datasheet for a 555 timer, you will find that pin 4 is generally called the RESET input. For most purposes, RESET is connected to V+ so that the timer won't reset.

    If the RESET input is less than about 0.8v, the timer will stop what it's doing and set the output pin high, and it'll stay that way until RESET goes back above 0.8v, or the power is turned off.
     
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  5. MrChips

    Moderator

    Oct 2, 2009
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    As I indicated in my other post on DeMorgan's Theorems, there are right and wrong ways of drawing logic gates and labeling signal names.

    Take for example a simple inverter. There are two ways to draw an inverter. Either the bubble is on the input or the bubble is on the output. Even though the bubble represents an inverter, it is not to be treated as such. The bubble indicates that the signal is ACTIVE-LO.

    In gate U1A below, the output is ACTIVE-LO.
    In gate U1B, the input is ACTIVE-LO.

    [​IMG]

    You should attempt to label the signals according to whether the signal is ACTIVE-HI or ACTIVE-LO as shown in both examples.

    (Caveat: Sometimes it is not possible to match up ACTIVE-LO signal with a bubble and vice-versa.)
     
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  6. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    Yes

    So if you have for example ""Active Low" input circuit. To activate the circuit you need supply the input with the specified LOW state voltage 0V. Then the circuit in is activate.
    But if you want to dis-active you circuit you supply the HIGH state.

    For example if we have ""Active Low" input we use pull-up resistor to ensure Idle HIGH state.

    Now, very carefully try to analyze this example

    [​IMG]

    And I hope that you understand it.
     
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  7. MrChips

    Moderator

    Oct 2, 2009
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    This is an example of where the OR symbol is inappropriate.
    The logic function is an AND of the control signal and the input signal.
    Hence the logic element should be drawn with an AND symbol with ACTIVE-LOW inputs and ACTIVE-LOW output.
     
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