MOVX A,@DPTR ; External Read, 16-bit address, RD* active
MOVX A,@Ri ; External Read, 8 -bit address, RD* active, for i = {0,1}
MOVX @DPTR,A ; External Write, 16-bit address, WR* active
MOVX @Ri,A ; External Write, 8-bit address, WR* active, for i = {0,1}
can u please explain me this part.......The falling edge of ALE allows a device called a transparent latch to capture the value of the P0 address bits at their value a short time (several nanoseconds) before the falling edge of ALE. This is called a setup time.
how i tell that if it is read or write process?When the rising edge of RD* happens the external RAM must have placed a byte of data on the P0 data bus. In a WRITE cycle the processor must have placed a byte of data on the P0 data bus to be written.
Yes, this my first time, actually it is in micro controller.In an external data memory access, either RD* will go low or WR* will go low. They cannot both go low on the same cycle. It is of course the case, most of the time, that neither one will go low. This means that the current instruction is NOT doing a READ or WRITE to external memory. All of this information is in the datasheets and the hardware manuals,I don't understand why this is so difficult for you. Is this your first experience with a processor bus?