Hi, all. I'm a old student who is learning again on Logic Design. This time, I want to know "timing methodologies", more clearly. My question is Given this situation [situation] register A ---->---- cpu ---->---- register A (it shows data flow.) , how is it possible that within the same clock cycle, data is read from and then written to register A after cpu processing(under rising edge triggered circumstance)? I believe that two rising edges are needed for this. Is my guess right? If so, one cycle period is from rising through falling to next rising? Sorry that my explanation is not good, hoping not to bother you. Thank you for reading. -------------- ps1. where can I get good information about timing? If you know, Could you let me know? ps2. In verilog, why is <= assignment used in coding a multiplexer instead of "=" assignment?