Discussion in 'General Electronics Chat' started by dalant019, Mar 21, 2010.

1. ### dalant019 Thread Starter New Member

Mar 21, 2010
1
0
Hi, all.
I'm a old student who is learning again on Logic Design. This time, I want to know "timing methodologies", more clearly.

My question is
Given this situation

[situation]
register A ---->---- cpu ---->---- register A
(it shows data flow.)

, how is it possible that within the same clock cycle, data is read from and then written to register A after cpu processing(under rising edge triggered circumstance)?

I believe that two rising edges are needed for this. Is my guess right? If so, one cycle period is from rising through falling to next rising?

Sorry that my explanation is not good, hoping not to bother you.

--------------
ps1. where can I get good information about timing? If you know, Could you let me know?

ps2. In verilog, why is <= assignment used in coding a multiplexer instead of "=" assignment?

Last edited: Mar 21, 2010
2. ### Wendy Moderator

Mar 24, 2008
20,772
2,540
Register A is an integral part of the CPU. They can't be separated cleanly. You might say it is even the core of the CPU, since the math and logic operations are designed around the registers, to measure, compare, and manipulate them.

The architecture of the CPU can vary a lot with the family. Your idea is valid, there were some families that used two clocks 90° apart (same frequency) to move things along.

3. ### rjenkins AAC Fanatic!

Nov 6, 2005
1,015
69
As Bill says, many processors use multi-phase clocks.

The Microchip PICs are a good example of this, a PIC running on a 20MHz oscillator only has a 5MHz instruction clock; each instruction clock cycle has four internal steps which allow the various data transfers and processing.

Some have higher multiples - the Z80 CPU (the original version at least) used a 12MHz clock for a 1MHz nominal instruction cycle.

Also, external bus or memory cycles often use both edges of the clock, or multiple stages through a cycle.

Have a look at Page 11 of this item for some example timing diagrams:
This (8051 CPU) also uses 12 oscillator cycles for one single bus cycle.
http://levkov.net/Proekt/Common/8051TTRL/Tutorial/Class5.pdf

Last edited: Mar 21, 2010