A Up|Down Counter

Discussion in 'Homework Help' started by dnkschn, Apr 12, 2009.

  1. dnkschn

    Thread Starter New Member

    Mar 29, 2009
    8
    0
    I'm trying to design a 3 bit signed up_down counter, it will have a clear input-which clears the counter, also set and enable inputs, when it is enabled(1), the set input will control the up or down.
    Since this is a signed counter, i need to show underflow and overflow as an output as well.
    Its a bit confused me. you have any suggestions to me?
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Grab a data sheet for a 74191.
     
  3. dsp_redux

    Active Member

    Apr 11, 2009
    182
    5
    How do you want to design it? VHDL? Only with FETs...? Logic Gates?
     
  4. dnkschn

    Thread Starter New Member

    Mar 29, 2009
    8
    0

    well thanks, but i designed it.
    Is it possible to write the vhdl code and then see the logic diagram of circuit? That sounds quite easy.
     
  5. electronictech

    Active Member

    Apr 1, 2009
    35
    0
    .

    Yes it is possible. Xilinx offers the 'ISE WEBpack' download for free. It is a big download, and you will have to sign up with Xilinx and register it.
    It is a bit intimidating to get started with, but if you follow the guided tutorials, you will get the hang of it quickly. The nice thing is that this software is everything in one, a development, simulation, and target programmer in one package.

    Anyways, have fun!
     
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