# A question about RS Flip-Flop

Discussion in 'General Electronics Chat' started by Deadeye the assassin, Oct 14, 2010.

Oct 14, 2010
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Good day

I'm fairly new to this, I'm currently earning my bachelor in computer science. The course has just started delving into logic gates and such which I think I understand well. But I'm having trouble understanding RS flip-flops, since according to the truth tables that I have seen only Q is remembered while NOT Q is just forgotten. But every time I look at the picture of the RS I get the nagging feeling that NOT Q should also be remembered since like Q it connects into an OR gate, I asked my teacher and he had no answer why this was.

Can anyone help me with this?

PS. I'm using the image on the wikipedia article for my assumption.

2. ### djsfantasi AAC Fanatic!

Apr 11, 2010
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Wikipedia states, "Normally, in storage mode, the R and S inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with ~Q the complement of Q. If S is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low even after R returns low".

This doesn't mean that ~Q is forgotten; it will always the the complement of Q and if Q is "remembered", so will ~Q

Oct 14, 2010
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So are you saying no matter what Q is there is always it's compliment present, for instance if Q is 0 then !Q is 1. Kind of boggles me that this is not in the truth table, since it seems to be quite important.
So would it make any difference if I would add !Q to the table?

And thanks for the speed response usually I have to wait 5-6 hours just to get an response

Mar 24, 2008
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