a problem About verilog hdl

Discussion in 'Programmer's Corner' started by Nec, Dec 30, 2008.

  1. Nec

    Thread Starter New Member

    Nov 21, 2008
    6
    0
    i have a project about programming a circuit with verilog,but i am callow about it.I wanna use if statement but it give error
    i define a variable called a and i use it like below

    if(a)------------>in this point,give parse error
    begin
    statement1
    statement2
    end------------>in this point,give parse error too

    where is the fault here?

    pls help me
     
    Last edited: Dec 30, 2008
  2. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Maybe you need a space between if and (a) and put ; after end.
     
  3. Nec

    Thread Starter New Member

    Nov 21, 2008
    6
    0
    first of all, thanks for your answer and i did but it didnt work and it give same errors.
     
  4. mik3

    Senior Member

    Feb 4, 2008
    4,846
    63
    Search for a user manual for your software which says how do you write the code exactly.
     
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