i have a project about programming a circuit with verilog,but i am callow about it.I wanna use if statement but it give error
i define a variable called a and i use it like below

if(a)------------>in this point,give parse error
begin
statement1
statement2
end------------>in this point,give parse error too

where is the fault here?

pls help me

 

Maybe you need a space between if and (a) and put ; after end.

 

first of all, thanks for your answer and i did but it didnt work and it give same errors.

 

Search for a user manual for your software which says how do you write the code exactly.