Hey guys, I'm currently doing some work on a synchronously digital circuit. Currently I have the outputs of both of an SRAM (CY62256) and a buffer (74LS244) connected on a bus.

I am using their Output Enable pins in order to control which is sending data on the bus (for the sake of the question lets ignore the write case).

My issue is that I am wanting to control both from a single clock (using an inverter, of course ). The frequency of which being ~1MHz. In doing so, there will be an overlap of 10 or so nanoseconds where they will both be trying to output on the bus. Is this acceptable, or am I going to have to tear up my clocking circuit so that they dont overlap at all?

Thanks,
Rob.

 

If your clock also controls the latching of data, yes. Latched data must always be stable before the clock.

 

Nope, the clock does not control the latching of data, there is a second clock that will fire later on that does that. This clock only controls which device has its outputs enabled.

Rob.

 

I'd use something like a 74LS138 (or half an LS139) as an address decoder to select which device is being accessed.
If it's on a CPU, use some of the higher order address lines to the Select inputs.

Connect the clock to the active-high enable and connect appropriate decoder outputs to the enables of the buffer and RAM.
Either ground the active low enables or use to cascade decoders.

That way, they (the devices) are only enabled during the second half (high) of the clock and there are no conflicts.

 

Thanks for the suggestion rjenkins, unfortunately that won't work.

The issue is that the CY62256 has a bi-directional bus. Before the rise of the clock the CY62256 is set to output mode, but at the rise of the clock I want the CY62256 to go to High-Z mode and the 74LS244 to go into output mode in order to get ready for Clock2 which will trigger the CY62256's WriteEnable pin.

The problem with a multiplexer/decoder is that the output of the 74LS244 won't be funnelled into the CY62256.

Rob.