I'm currently designing my 9-0 counter for my project.
I simulated my design and the output is just 9,8,5,4,1,0 i think my j2 and k2 has a problem.
Kindly check my work sir.

 

Your circuit worked when I simulated it.

Check/post your simulation.

 

You have J1 = Q1'. Q0' . (Q2 + Q3)

Since this is the Q1 J-K flip-flop this becomes

J1 = Q0'.(Q2 + Q3)

 

Your circuit worked when I simulated it.

Check/post your simulation.

Here's my simulation sir, it didnt worked. 9,8,5,4,1,0

 

You have J1 = Q1'. Q0' . (Q2 + Q3)

Since this is the Q1 J-K flip-flop this becomes

J1 = Q0'.(Q2 + Q3)

sir what rule did you used to simplify j1?

 

BTW this is a 9-0 counter, my thread subject is wrong my bad sir.

Edit: Title corrected to show 9-0 Counter using J-K flip-flop.

 

sir what rule did you used to simplify j1?

I used this:

The characteristic equation of the JK flip-flop is:

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

 

oh tnx a lot sir, how about my circuit or k mapping? I simulated it using Logism, its not working. It keeps on skipping 7,6,3,2 those state has a high Q2 output.

 

Then obviously, check your J and K inputs to Q1.

You forgot to connect Q0' to K1

 

Yup, you missed the \(\overline Q_{0}\) to \(K_{1}\) connection...

 

Yay. Thank you so much sir. More I2R to this site.

 

Now try removing Q1' from the J1 expression.