8255 memory mapping

Discussion in 'Embedded Systems and Microcontrollers' started by Tera-Scale, Sep 9, 2011.

  1. Tera-Scale

    Thread Starter Active Member

    Jan 1, 2011
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    hi, I am a little bit confused about how the 8255 Ports are mapped: PA - 0x4000, PB - 0x4001, PC - 0x4002, PCNTRL - 0x4003. 4002H is 0100 0000 0000 0010B. Is this considered as a conrol word? how come it is 16-bit? Any hint would be really appreciated. The only think I can understand is the selection of the Ports with last 2 bits.
     
  2. bertus

    Administrator

    Apr 5, 2008
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  3. t06afre

    AAC Fanatic!

    May 11, 2009
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    If it is memory mapped. You must have some sort of address decoding using the higher end of the address bus. This will be used via some decoding circuitry to enable your 8255 (pull the CS pin low on the 8255). Then the A0 and the A1 of the address bus. In your host system is connected to the A0 and A1 pin of your 8255. Then the CS pin of your 8255 is pulled low. It will be the owner of the data bus.
     
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  4. Tera-Scale

    Thread Starter Active Member

    Jan 1, 2011
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    Do these hex point to memory locations in 8051 memory? If yes, how can I deduce the addresses for the specific PPI ports?
     
  5. RRITESH KAKKAR

    Senior Member

    Jun 29, 2010
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    Tera, are you working on 8085 up's ??
     
  6. t06afre

    AAC Fanatic!

    May 11, 2009
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    It is very simple. And you have actually answered the question your self.
    Then using memory mapped IO. The different processor auxiliary units share the total memory address range.
     
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