What are the different methods in which IO devices can be addressed in 8085 based design?

 

There are only two.

1. Memory mapped
2. I/O mapped

A memory mapped peripheral occupies a portion of th 64K memory space. As such it can be accessed with the same instructions that you would use to access memory. An I/O mapped peripheral uses the IN and OUT instructions, to read and write data from the data bus.

So how do you know the difference? Well pin 34 called IO/M* is high for an I/O access via the IN or OUT instructions, and it is low for an access to memory.

A 74xx32 OR gate would be used to combine IO/M* and RD* for a READ strobe to memory and a 74xx32 OR gate would be used to combine I/O/M* and WR* for a write strobe to memory.

To make the I/O strobes you could invert IO/M* and then use the 74xx32 to combine it with RD* and WR* to make the coresponding IO Read and IO Write strobes.

You could also do clever things with a 74xx138 or 74xx139 or the new configurable gates like the 74LVC1G97.

 

Thank u for the answer....if u don't mind can i ask u some more qns on 8085...plz.


The program memory in 8085 must be present in the address space starting at 0x0000.why?
Is there any way of disabling TRAP interrupt???(I know it is non-maskable interrupt)
Bus mastership mechanism supported by 8085.


can u plz suggest me some books for 8085(other than Gaonkar....I read it)

 

1. Program memory must be present at address 0x0000 because that is where the porcessor goes to start fetching instructions after RESET_IN* (pin 36) is released. I believe that if there is no memory at location 0x0000 that the data buss will return an 0xFF which is an RST 7 instruction. This will then go to locatio 0x0038 with predictable results.
2. Just put the proper return instruction at the appropriate location, or tie the TRAP (pin 6) high or low as appropriate so that a TRAP condition never occurs.
3. The HOLD (pin 39) and HLDA (pin 38) are used to request bus mastership. The hold state will not be released until HOLD goes low.

I never heard of Gaonkar, never read it. I always start with the manufacturers datasheets.

http://www.engineer.gvsu.edu/students/part_inventory/p8085ah.pdf

Don't know if they are still available on the Intel website. NOT

Instruction set reference
http://ce.sharif.edu/~a_eslamifar/instructionset8085.pdf

Don't know why you need me to do your google searches for you.

 

Sorry....I searched them in the google but i did not get them ......


Thank u for the answers

1. Program memory must be present at address 0x0000 because that is where the porcessor goes to start fetching instructions after RESET_IN* (pin 36) is released. I believe that if there is no memory at location 0x0000 that the data buss will return an 0xFF which is an RST 7 instruction. This will then go to locatio 0x0038 with predictable results.
2. Just put the proper return instruction at the appropriate location, or tie the TRAP (pin 6) high or low as appropriate so that a TRAP condition never occurs.
3. The HOLD (pin 39) and HLDA (pin 38) are used to request bus mastership. The hold state will not be released until HOLD goes low.

I never heard of Gaonkar, never read it. I always start with the manufacturers datasheets.

http://www.engineer.gvsu.edu/students/part_inventory/p8085ah.pdf

Don't know if they are still available on the Intel website. NOT

Instruction set reference
http://ce.sharif.edu/~a_eslamifar/instructionset8085.pdf

Don't know why you need me to do your google searches for you.

 

Basically addressing any peripheral device in a system, be it a simple uP to any higher complex configuration, what is required is to partition the available
memory / io space into suitable blocks of digital binary values , such that each device has its own unique address code. This unique address may be in memory area or seperate io area , the allocation depends on the designer to carve the unique address from the hardware resources available, amount of memory , no. of io peripherals used. Whether it is mem or io mapped does not matter for properly designed small systems.
The main point to keep in mind is that the address allocation should be such that any software / hardware glitch ideally must not cause any wrong device to be accessed. To this extent suitable decoder logic chips together with software control on the decoder can be used.
In any given chip , where the first byte of program after system reset
depends on the chip designer. Typically it will be at 0000 or at ffff.
The trap or any other interrupt vector addresses are also at the hands
of chip designer. Basically they are fixed address where the program execution will branch to if the said interrupt/s are enabled. These locations are a few bytes long , where the software/ firmware programmer inserts suitable instruction / address to make the program jump to the desired interrupt routine. Most of the interrupts have software systems called masks to enable / disable the same as required. For external hardware interrupts e.g. trap - nmi , this feature can be disabled in hardware , by tying this pin
to Hi / Lo , whichever is the inactive level for the same. The NMI refers to the software masking option which is not available for this interrupt. If you want to use the NMI for certain aspects disable the same for others, the same will have to be done in hardware , with suitable gates addressed as a perpheral which can be enabled / disabled using software .