8085 address question.....

Discussion in 'Programmer's Corner' started by RRITESH KAKKAR, Sep 14, 2011.

  1. RRITESH KAKKAR

    Thread Starter Senior Member

    Jun 29, 2010
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    Alright, I have decoded A15 A14 A13 to single 8 bit addr by 74138 ( 3 to 8 decoders).
    My PROM is of 8Kbytes and RAM is also same ( 2864 & 6264) the PROM is set at 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH from Y2 of 74138 chip to chip select of memory IC....

    The problem is that,i don't understand why other pin of 74138 decoder are working, mean only Y0 and Y2 should give output as i am using only these addr 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH...

    please clear my doubt, by putting some light of your experience...
     
  2. t06afre

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    May 11, 2009
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    The output from the 74xx138 is active low if I remember correct. Chip select is most often(99.99%) active low on processor auxiliary for cores like the 8085 and the Z80
     
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  3. RRITESH KAKKAR

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    This is not answer of my question, here i am asking why the program counter is running on other addr bits as i am using only 0000H to 1FFFH by chip enable of Yo of 74138 chip and RAM at 4000H to 5FFFH...??
     
  4. t06afre

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    If you do anything wrong then laying out (or soldering up) the address or data busses error like this may occur. I spent/wasted one week many many years ago. Then I mirrored the address buss on a Z80. I was making on a vero-boad. The error was much like the one you describe. Erratic address and data busses
     
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  5. nigelwright7557

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    May 10, 2008
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    I dont know about the 8085 but the Z80 outputs refresh addresses for DRAM all the time.
     
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  6. t06afre

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    yes that is correct for the Z80, but this is valid only for the lower 7 bits of the adress buss. The rest do not change.
     
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  7. Papabravo

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    Feb 24, 2006
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    If there is supposed to be a valid address on the bus for every cycle you might expect that to be the case. If on the other hand the address bus assumes an arbitrary state when there is no fetching to do then it is quite possible that you may see other addresses. What you won't see is valid strobes for the data like RD* and WR*
     
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  8. t06afre

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    Most assemblers from that period default the code to start at adress 0x100h if you do not use the org statement in your code. The reason is that the lower address range was used for the CPU ISR coding. For both Z80 and 8085 I think
    Can you post your current assembler code
     
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  9. Papabravo

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    Feb 24, 2006
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    Doesn't matter what the code is used for. The question was "if all the instruction fetches are in the 8K range from 0x0000 to 0x1FFF(Y0-low), and all the data fetches are from the 8K segment from 0x4000 to 0x5FFF (Y2-low), then why are the other outputs of the decoder going low".

    The answer revolves around what the address bus is doing when it is neither fetching an instruction nor reading and writing data. In particular what are inputs A, B, and C of the decoder doing, and further what are the G1, G2A, and G2B enables doing?

    PS -- I'm really trying to get the OP to answer his own question, but I'm not having much luck.
     
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  10. t06afre

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    Yes the person closest to find the error is the OP him self. Perhaps a microcontroller project would be better for him. Since a microcontroller after all is in principle a pre wired microprocessor system on chip. I think perhaps the OP should leave this project for now. And take it up again then he has become more experienced. Such a project is not for beginners.
     
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  11. RRITESH KAKKAR

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    Thanks for saying this....
    Now i think 8085 is cool project
     
  12. RRITESH KAKKAR

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    OK, I am using G1 connected to GND and G2A and G2B to Vcc.. as per data-sheet..
    The ABC pin of 74138 is connected to A15 to C A14 to B and A13 to A
     
  13. RRITESH KAKKAR

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    Code of 8085 for output at SOD ............

    Code ( (Unknown Language)):
    1. ;Flash a LED on SOD
    2. ;Top of RAM @ 0x4000
    3.  
    4. START:  LXI H, 4000h
    5.                 SPHL
    6.  
    7. FLASH:  MVI A, 0C0h
    8.         SIM
    9.         CALL DELAY
    10.         MVI A, 40h
    11.         SIM
    12.         CALL DELAY
    13.         JMP FLASH
    14.  
    15. ;Delay, return to HL when done.
    16. DELAY:  MVI A, 0FFh
    17.                 MOV B, A
    18. PT1:    DCR A
    19. PT2:    DCR B
    20.                 JNZ PT2
    21.                 CPI 00h
    22.                 JNZ PT1
    23.                 RET
     
  14. Papabravo

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    Feb 24, 2006
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    I think you have this backwards.
    G1 is an active high enable -- tie it to VCC
    G2A and G2B are active low enables -- tie them to GND
     
  15. Papabravo

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    Feb 24, 2006
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    0x4000 is a really crappy place to put your stack pointer. When you call delay it will try to push the return address to 0x3FFF and 0x3FFE. The DELAY routine will execute up to the return instruction then it will try to return to the address at 0x3FFF and 0x3FFE. Problem is that since there is no memory there the PC will be loaded with garbage and off you go into the weeds.

    The stack pointer (SP) should be initialized to 0x5FFF for absolute safety. Sure this will waste a byte since the SP is decremented before any data is stored. After you get things working you can experiment.
     
  16. stahta01

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    Jun 9, 2011
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    FYI:

    The IO/M* pin (likely pin 34) likely needs hooked up to the 74138; when that pin is low then the 8085 is accessing memory. When high it is doing a non regular memory operation.
    It is doing IO operation instead.

    Tim S.
     
  17. tgotwalt1158

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    Feb 28, 2011
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    I think your address selection range is not correct. For Yo, should be F0000~F1FFF and for Y2, should be F4000~F5FFF. If it does not work, then
    there may be some coupling going on at enable and input select. Another way is to use 74139 instead of 74138 and cascade the outputs.
     
  18. t06afre

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    The reset vector for the 8085 is 0x0000h So putting the ROM in the lower part is correct. I also think the I/M* pin of the 8085 is not needed if the system use memory mapped IO with decoding. This may simplify the design somewhat. I think this thread is going nowhere as the OP has not provided any schematics for the current setup. As he has put the design on a vero-board some schematics have to exist.
     
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  19. RRITESH KAKKAR

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    Sorry, i wrote this in hurry...
    the G..pin are connected right as per data sheet.
     
  20. RRITESH KAKKAR

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    Jun 29, 2010
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    Who to do this and why??
    The stack pointer (SP) should be initialized to 0x5FFF for absolute safety.
     
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