8051 square wave generation

Discussion in 'Embedded Systems and Microcontrollers' started by aslanpeter, Aug 17, 2010.

  1. aslanpeter

    Thread Starter New Member

    Aug 17, 2010
    2
    0
    Heya,
    I was reading the book: 8051 micrcontrollers, authir david calcutt and i am not sure about my understanding to section 1.8: Microcontroller clock. The author gave this code


    Code (Text):
    1.  
    2.           $INCLUDE (REG66X.INC) ; lists all sfr addresses          
    3.           ORG 0 ; sets start address to 0          
    4.           SJMP START ; short jump to START label          
    5.           ORG 0040H ; putsnextprogram line at address 0040H
    6. START: JB P1.0,PULSE ; jump to PULSE if pin 0, port 1 is logic 1            
    7.            CLR P1.7 ; otherwise clear pin 7 port 1 to zero            
    8.            SJMP START ; go to START check switch
    9. PULSE: SETB P1.7 ; set pin 7 on port 1 to logic 1            
    10.            CLR P1.7 ; clear pin 7 on port 1 to logic 0            
    11.            AJMP START ; go to START check switch          
    12.              END ; no more assembly language
    13.  
    under the assumption that




    SETB takes 6 microcontroller clock cycles CLR takes 6 microcontroller clock cycles AJMP takes 12 microcontroller clock cycles JB takes 12 microcontroller clock cycles
    the author concludes that SETB is held for 6 clock cycles and CLR is held for 30 clock cycles. the output waveform is shown in Figure 1.12:
    +-------+-----+---------+-----------+-----+
    ..setB....CLR.....AJMP........JB..........setB
    ....6........6..........12...........12..........6

    setB : for 6 cycles, the logic is one
    CLR: for 6 cycles, the logic is zero
    AJMP: for 12 cycles, the logic is zero
    JB: FOR 12 cycles the logic is zero
    SETB: for 6 cycles the logic is one

    I want just to make sure i am getting the timing correct. I believe that the line will switch to logic 1 after the execution of setB to completion. Hence it will be one during the CLR instruction exection. it remains 1 until CLR finishes its operation. then it switches to 0 and remains at this level until the next instruction: AJMP finishes. this takes 12 cycles, then there is a jump to strt and execution of JB, THEN THE jump to PULSE label. the line won't get one until setB is completed. Hence we should have something like this:

    +-------+---------+-----------+-----+-----+
    ...clr........AJMP ......JB...........setB....clr
    ....6............12........12............6.......6

    CLR: for 6 cycles, the logic is one
    AJMP: for 12 cycles, the logic is zero
    JB: FOR 12 cycles the logic is zero
    SETB: for 6 cycles the logic is zeru
    clr : for 6 cycles, the logic is one



    I know we end up having the same waveform cuz clr and setB consumes the same number of cycles but want to make sure i am getting the timing right. another question, what about when the change to the logic level occurs before the end of the last cycle, e.g. setb happens at clock cycle 4 as 4, and 5 are dummies. should we take care of this as well? I can't find the exact timing of the machine cycle of the different instructions
    cheers
     
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