For the past year or two, I've been designing an 8-bit computer mainly consisting of TTL and CMOS 74HC and 74LS series chips. It's called the SCHM8BF001 computer architecture and my current stage is at the construction of the SCHM8B1001 CPU. And no, I'm not building it all from NAND gates and please don't go into the impracticalities of building such a device as it has been quite a help in testing my problem solving skills for developing various speed applications in hardware for the device.
I already understand that I will be needing some pull-up resistors for the 74LS outputs (perhaps suggest a good value I could use? I currently have a bunch of 10K Ohm 1/4 Watt resistors which might be sufficient.
Anyways, I have 21 breadboards stuck onto a wooden panel and most of the spaces have been filled with the chips I will be needing. Some of the chips are being removed, replaced or rewired as I encounter problems or come up with improvements.
My design includes an Instruction Register (implemented with a CY7C130 DIP dual port SRAM), a program PC and an 8 bit adder (two 74LS83s) connected to the output (keeps the second address ahead by one at all times (necessary for instruction set output and running cycle)), including the necessary circuitry for a 1 clock per instruction cycle (running at 8 MHz with an auxiliary 16 MHz clock attached to a 4-bit binary counter as a frequency divider).
Other aspects include a decoder which I am currently developing to accommodate the second version of my instruction set. Along with a D Register (data), AD Register (address data), CD Register (control data), and a C Buffer (control opcode expansion buffer), the device is outfitted with a 32-bit shift register (high speed long multiplication operations with 8 to 16 bit signs including overflow and underflow registers for quick 32 to 64 bit sequential cascading, *implemented with 8 74HC194 4-bit bidirectional shift registers), PC1 and PC2 24-bit address program counters (uses 6 bidirectional 74HC193 4-bit counters), and a 32-bit Incrementer/Decrementer (used to increment and decrement variables. Will gain the ability to be separated into two separate 16-bit counters. Uses 8 74HC193s). Other devices include the ALU with it's A, B and C registers whose functions are implemented using two cascaded 74181 4-bit ALUs, carry register for quick multi-signed cascading, and finally, the CLU (conditional logic unit) which interprets the output of the ALU to produce a Boolean result based on A == B, A != B, A < B, A > B, A <= B, A >= B, whose signals are perceived when setting the ALU to A minus B minus 1 (no carry input).
Now, the main problem is with the Incrementer/Decrementer which no matter what, must be able to increment and decrement it's values. The PC1 and PC2 were supposed to be up/down counters but they can remain as up counters using the 74HC161 binary counter. The advantage with the 74HC161 is that it has count enable pins which are necessary in synchronous cascading where all the chips are connected to the same clock. That way, you can synchronously cascade them with no additional chips except the output enabling 74HC541 buffers.
The problem with the 74HC193 up/down counter is that it doesn't have a count enable pin and can only be cascaded using ripple carry. If it was two counters alone, then I would have the problem with the delay as we only have the delays of the first and second chip. The same goes with two 74HC161 chips, synchronous or not. But after that with the addition of more chips, the counter using 74HC161s in synchronous cascading will have a maximum delay of two chips. 8 74HC193s using asynchronous cascading would simply take two long as it only has 125 ns (within an 8 MHz cycle) to produce a result and there is also the delay of the decoder itself.
I do have a way to synchronously cascade these chips using the !PL pin and through regulating whether the chip's output goes back to it's own input (if the load enable is activated, it will load it's own value, thus retaining it's value until the load enable is deactivated (like a count enable)). For the first counter, the !TCU and !TCD (terminal up and down count pins) are attached to a 74HC00 NAND gate and it's output to the !PL pin of the next most significant chip. A buffer will be included to disable it's signal when the machine code program is loading a byte into the counter. But for various reasons, there were a huge number of things wrong with the edit I came up with concerning the conflicting isolation and connection between pins.
E.g. in one instruction, the !PL pins/count enables of the binary counters need to be separate so that the binary counter can function, but in another, each pair of chips need their !PL pins connected in order to load a byte.
Then we have the connection from the output enable buffer back to the input. The outputs of those buffers are all connected together and so are the inputs of the counter and I didn't realize this (I will include a schematic when I have time and if it is needed). I have a solution that uses additional buffer, but that will require 8 more 20 pin chips for the Incrementer/Decrementer alone. Hence, I will be leaving the PC1 and PC2 only as a single direction counter with the 74HC161s cascaded synchronously.
So if anyone has any ideas on how to cascade 8 74HC193s together synchronously without adding too many chips or maybe even none, please share as this has been stunting my work for a while and I intend on executing it's first instruction before the end of the summer break.
I will post the schematics if necessary.
I already understand that I will be needing some pull-up resistors for the 74LS outputs (perhaps suggest a good value I could use? I currently have a bunch of 10K Ohm 1/4 Watt resistors which might be sufficient.
Anyways, I have 21 breadboards stuck onto a wooden panel and most of the spaces have been filled with the chips I will be needing. Some of the chips are being removed, replaced or rewired as I encounter problems or come up with improvements.
My design includes an Instruction Register (implemented with a CY7C130 DIP dual port SRAM), a program PC and an 8 bit adder (two 74LS83s) connected to the output (keeps the second address ahead by one at all times (necessary for instruction set output and running cycle)), including the necessary circuitry for a 1 clock per instruction cycle (running at 8 MHz with an auxiliary 16 MHz clock attached to a 4-bit binary counter as a frequency divider).
Other aspects include a decoder which I am currently developing to accommodate the second version of my instruction set. Along with a D Register (data), AD Register (address data), CD Register (control data), and a C Buffer (control opcode expansion buffer), the device is outfitted with a 32-bit shift register (high speed long multiplication operations with 8 to 16 bit signs including overflow and underflow registers for quick 32 to 64 bit sequential cascading, *implemented with 8 74HC194 4-bit bidirectional shift registers), PC1 and PC2 24-bit address program counters (uses 6 bidirectional 74HC193 4-bit counters), and a 32-bit Incrementer/Decrementer (used to increment and decrement variables. Will gain the ability to be separated into two separate 16-bit counters. Uses 8 74HC193s). Other devices include the ALU with it's A, B and C registers whose functions are implemented using two cascaded 74181 4-bit ALUs, carry register for quick multi-signed cascading, and finally, the CLU (conditional logic unit) which interprets the output of the ALU to produce a Boolean result based on A == B, A != B, A < B, A > B, A <= B, A >= B, whose signals are perceived when setting the ALU to A minus B minus 1 (no carry input).
Now, the main problem is with the Incrementer/Decrementer which no matter what, must be able to increment and decrement it's values. The PC1 and PC2 were supposed to be up/down counters but they can remain as up counters using the 74HC161 binary counter. The advantage with the 74HC161 is that it has count enable pins which are necessary in synchronous cascading where all the chips are connected to the same clock. That way, you can synchronously cascade them with no additional chips except the output enabling 74HC541 buffers.
The problem with the 74HC193 up/down counter is that it doesn't have a count enable pin and can only be cascaded using ripple carry. If it was two counters alone, then I would have the problem with the delay as we only have the delays of the first and second chip. The same goes with two 74HC161 chips, synchronous or not. But after that with the addition of more chips, the counter using 74HC161s in synchronous cascading will have a maximum delay of two chips. 8 74HC193s using asynchronous cascading would simply take two long as it only has 125 ns (within an 8 MHz cycle) to produce a result and there is also the delay of the decoder itself.
I do have a way to synchronously cascade these chips using the !PL pin and through regulating whether the chip's output goes back to it's own input (if the load enable is activated, it will load it's own value, thus retaining it's value until the load enable is deactivated (like a count enable)). For the first counter, the !TCU and !TCD (terminal up and down count pins) are attached to a 74HC00 NAND gate and it's output to the !PL pin of the next most significant chip. A buffer will be included to disable it's signal when the machine code program is loading a byte into the counter. But for various reasons, there were a huge number of things wrong with the edit I came up with concerning the conflicting isolation and connection between pins.
E.g. in one instruction, the !PL pins/count enables of the binary counters need to be separate so that the binary counter can function, but in another, each pair of chips need their !PL pins connected in order to load a byte.
Then we have the connection from the output enable buffer back to the input. The outputs of those buffers are all connected together and so are the inputs of the counter and I didn't realize this (I will include a schematic when I have time and if it is needed). I have a solution that uses additional buffer, but that will require 8 more 20 pin chips for the Incrementer/Decrementer alone. Hence, I will be leaving the PC1 and PC2 only as a single direction counter with the 74HC161s cascaded synchronously.
So if anyone has any ideas on how to cascade 8 74HC193s together synchronously without adding too many chips or maybe even none, please share as this has been stunting my work for a while and I intend on executing it's first instruction before the end of the summer break.
I will post the schematics if necessary.
