Hi,

Can you design a 8 bit magnitude comparator with using only simple 2x1 MUX with minimum logic gates?

 

A parallel 8-bit magnitude comparitor requires simultaneously operating on 16 bits of data. Muxes only allow you to look at half the data at a time, so do not seem well suited.

A serial magnitude comparator, where a pair 1 of 8 bits are selected out of the two 8 bit bytes, could utilize a tree of muxes.

 

A parallel 8-bit magnitude comparitor requires simultaneously operating on 16 bits of data. Muxes only allow you to look at half the data at a time, so do not seem well suited.

A serial magnitude comparator, where a pair 1 of 8 bits are selected out of the two 8 bit bytes, could utilize a tree of muxes.

I mean, I made it with 70-80 MUXes, i want to decrease the number,

 

I mean, I made it with 70-80 MUXes, i want to decrease the number,

Why would you want to? Is this homework?

 

Why would you want to? Is this homework?

It's a question from somebody, but we will decide the minimum number of 2x1 muxes

 

You should not need THAT many muxes to do the job.
You probably could make a unit that compares one bit position strating with MSB, if one bit is higher than that number wins, if they are the same you enable the next stage, repeat until you reach LSB.

 

You should not need THAT many muxes to do the job.
You probably could make a unit that compares one bit position strating with MSB, if one bit is higher than that number wins, if they are the same you enable the next stage, repeat until you reach LSB.

I finally reduced the number to the minimum I think.

I managed to implement it with 23 MUXes.

 

Care to show your schematic?

 

Just my 2 cents...not entirely relevant:

A NAND gate can be built with two 2:1 muxes. Therefore, any logic function can be realized by a combination of 2:1 muxes.