Okay, to some this question may seem silly; however, I have been in a full study of the "guts" of the 741 op amp. At one point in my study I (so to speak) tore into the inner workings of the 555. Now, I am into the 741. Now, I understand most of the circuitry. I can understand the current mirror parts, the amplifier sections (gain stage), the differential stage, and such. BUT, my question is about the inputs themselves. You see, before I looked into the schematic of this little "beastie," I had in my mind a possible "schematic" of what the inputs might be, based upon their descriptions: Inverting and Non-inverting inputs. That is to say, for the non-inverting inputs I had IC formed BJTs configured as either common collector or common base since that would not invert the input signals. Okay, well and good so far. In fact, the "guts" do reveal a common collector (emitter follower) configuration. All is well....so far. The world is beautiful and makes sense. Then, I was tossed a curve ball that I totally fumbled. The invert input I wild-eyed speculated would be the common-emitter configuration....after all, it does invert the output signal. HOWEVER, no dice. I still had the (as you all know) the common collector/emitter follower staring at me. Okay, by now you see my reason for confusion. How can this emitter follower be the inverter input?!? As I have gone through the "innerds" of this monster (the 741 op amp, that is), what have I missed? Is there a section I missed dedicated to the output of the non-invert pin input? Is there another section dedicated to the output of the invert pin input? I didn't see any. In fact, I did trace an invert section (common emitter if memory serves) in the (I think it was....I don't have the schematic in front of me)...but I think it was in the Gain Stage. Might have been in the Bias Generator....but, I think the common emitter inverting occurred in the Gain Stage. Anywho, can someone explain or refer to materials that better explain to me how a common-collector amplifier configuration is going to invert the invert pin's input? AND, there is always an "and" or a "but" isn't there?....moreover, can someone explain how that common-emitter configuration in the Gain Stage (?) isn't going to invert the non-invert pin's input signal?