7-Seg Clock using only logic gates and Flip Flop

Discussion in 'General Electronics Chat' started by kompteck, May 4, 2010.

  1. kompteck

    Thread Starter New Member

    May 4, 2010
    8
    2
    OK this is my first post here and hope to contribute in the future. Right now hopefully someone here and help me out here.

    Ok heres the project im trying to do and the problem Im having.

    Idea:
    Im trying to make a 7-segment clock using only logic gate and flip flops fully inside a CPLD.

    Problem:
    So far im doing the ones place for the minutes section of the clock. I got my basic next state equations and the combinatorial logic part built, example for the logic if I put in 1111110, then 0110000 comes out as expected from my equations. The problem lies when I add the flip flips to the logic part. In my set up the first state isnt 0000000 so I have to preset and clear the FF's to get the counter started but that said the FF's cant accept the next value because they are not set to accept the next values due to the preset and clear values set. The FF's present and clear need to be changed to VCC after the first clock edge and stay the way indefinitely. I have been trying to add things to the P/C's pin (where the GND is in the attached pic) but havent been able to get it to work.

    Anyone have any ideas on how to fix this? I have one but it would require a whole new design.

    I using the standard A,B,....,G as the labeling of the led's

    Next State
    A B C D E F G | A+ B+ C+ D+ F+ G+
    ------------------------------------
    1 1 1 1 1 1 0 | 0 1 1 0 0 0 0 Zero => One
    0 1 1 0 0 0 0 | 1 1 0 1 1 0 1 One => Two
    1 1 0 1 1 0 1 | 1 1 1 1 0 0 1 ....
    1 1 1 1 0 0 1 | 0 1 1 0 0 1 1
    0 1 1 0 0 1 1 | 1 0 1 1 0 1 1
    1 0 1 1 0 1 1 | 1 0 1 1 1 1 1
    1 0 1 1 1 1 1 | 1 1 1 1 1 1 1 ....
    1 1 1 1 1 1 1 | 1 1 1 1 0 1 1 Eight => Nine
    1 1 1 1 0 1 1 | 1 1 1 1 1 1 0 Nine => Zero
     
  2. kingdano

    Member

    Apr 14, 2010
    377
    19
    how have you coded this in the CPLD?

    i am fairly sure that this would require coding a state machine - and that doing so would have the software synthesize the necessary flip flops.

    this is a good example of coding a FSM (finite state machine) and to me that seems to be the most logical (no pun intended) way to do this.

    http://www.altera.com/support/examples/verilog/ver_statem.html
     
  3. kompteck

    Thread Starter New Member

    May 4, 2010
    8
    2
    Yes that sounds like a excellent idea but I haven't learned enough about VHDL to attack this problem that way yet.

    I am using Quartus and just doing everything with the block diagrams and symbols.

    If I could just figure out how to stick those pins to VCC after the first clock cycle this would work just fine.
     
  4. kompteck

    Thread Starter New Member

    May 4, 2010
    8
    2
    Well for those interested I as able to get it working but only after a total redesign. I ended up making a binary decoder. I have attached my design for those who might find it useful.

    I have attached the design files. I used VHDL and some FF's. I did not supply the code but I did attach the block diagram realized from the VHDL and FF schematic diagram.
     
  5. retched

    AAC Fanatic!

    Dec 5, 2009
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    Well that didn't take very long.

    You must have drive.
     
  6. kompteck

    Thread Starter New Member

    May 4, 2010
    8
    2
    LOL yeah I guess you could call it that... I just could sleep last night so I did the redesign last night at about 5am.
     
  7. kingdano

    Member

    Apr 14, 2010
    377
    19
    yikes.

    5 am verilog session...


    edit: VHDL, not verilog, my bad.

    in all seriousness though, you should try to avoid "coding" the CPLD using schematic entry in the future, it is an inefficient way to code things and may use more resources than required.

    most compilers are smart enough to reduce your schematics complexity if possible though - but it is still not good practice.

    kudos for the effort though, well done.
     
  8. kompteck

    Thread Starter New Member

    May 4, 2010
    8
    2
    Thanks. Im just learning this stuff. Ive only been using Quartus for a semester. The combinational logic was done in VHDL then I added the FF's. Im sure once I get more experience I'll be able to do the whole thing in code. So far though Quartus seems to do a pretty good job at reducing the cell count when I compile. I can watch it drop as it get compiled.

    If anyone is interested I'll post the whole project when I complete it.
     
  9. retched

    AAC Fanatic!

    Dec 5, 2009
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    That would be good for any future students or anyone who in interested in this.

    Thanks.
     
  10. Vijay Parishith

    New Member

    Apr 6, 2016
    1
    0
    hey mate i and doing the same project could you please help me out
     
  11. dl324

    Distinguished Member

    Mar 30, 2015
    3,242
    619
    Welcome to AAC!

    Did you notice the red warning telling you that you were replying to a very old message?
    Are you really limiting yourself to flip flops and logic gates?
     
  12. cmartinez

    AAC Fanatic!

    Jan 17, 2007
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    I suggest you download a digital circuits simulator. Such as digital works, which is rather easy to use.
     
  13. GopherT

    AAC Fanatic!

    Nov 23, 2012
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    Look at Post #1 again,

    The OP didn't state how he was approaching the problem, how far along he was, where he was stuck... he just said, "...please help me out". Why teach a man to fish if he clearly wants to buy a tasty McDonald's Filet-O-Fish sandwich.

    EDIT:
    It is also possible that he is expecting someone to give him a tasty McDonald's Filet-O-Fish sandwich.
     
    absf likes this.
  14. absf

    Senior Member

    Dec 29, 2010
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