6bit Linear Ramp Analogue to Digital Converter

Discussion in 'Homework Help' started by camjerlams, Oct 29, 2013.

  1. camjerlams

    Thread Starter Member

    Dec 23, 2012
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    1
    Hi, I have this question and I'm unsure of what to do.. I'm guessing I need 6 flip flops and a clock, I just can't visualise what i need to do..
    Can anyone give me a hand?

    Your objective is to implement a 6bit Linear Ramp Analogue to Digital Converter

    Your implementation should be on a single AND OR Gate Array
    (Programmable Logic Array) with an appropriate number of registers.

    Your circuit takes as its input a voltage v between 0.0V and 6.3V and returns a number which is n=ceiling(10v).

    Assume that your input voltage remains within the specified range.
    The following analogue system mare available:

    1. An 8bit Digital to Analogue Converter with vout=0.1n, where n is an 6 bit unsigned binary integer. You do not need to specify the design of the Digital to Analogue Converter.

    2.
    A comparator which operates effectively for the input voltage range, and
    provides a digital logic output. You do not need to specify the design of the Comparator, but you will need to specify the conditions under which
    the output is TRUE versus FALSE.
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    What efforts have YOU made to solve YOUR homework problem?

    You might start with reading up on how a linear ramp ADC works.
     
  3. camjerlams

    Thread Starter Member

    Dec 23, 2012
    56
    1
    Fair enough. I know that the counter is connected to a DAC, the DAC output goes to comparator to compare to current input, comparator gives true when it needs to display number and reset count.

    I can draw how it goes together, dont know about the logic array, where does it go? If i didnt have to multiply the output by ten would I need logic gates?
     
  4. camjerlams

    Thread Starter Member

    Dec 23, 2012
    56
    1
    Can I do it without drawing out a truth table of 63 terms?
     
  5. WBahn

    Moderator

    Mar 31, 2012
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    You don't have to multiply anything. You need the DAC configured so that for a given input n it outputs a voltage that is 0.1V/lsb (n effectively has units of lsb). That way when n is 63, the DAC will output 6.3V. Notice that the assignment specifically tells you that you can assume you have a DAC which is configured exactly that way.

    So put together an "event pipeline", which just a fancy term for a description of what happens from start to finish in very explicit detail. It's not enough to say things like, "comparator gives a true when it needs to display a number". It needs to be stated at the level of detail compatible with the tools available to make it happen. So something like, "If the comparator output is true, then the present value of the counter is latched in an output register whose output is continuously displayed." But then you need to describe what is meant by "displayed"? There is no mention of any kind of a display in the list of resources you have to work with.
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    Yes, you can do it without enumerating a truth table. Descriptions in terms of what the truth table elements represent should suffice nicely.
     
  7. uwotm8

    New Member

    Oct 29, 2013
    7
    0
    Same class, same issue.
    I understand how the ADC works.

    Counter -> DAC -> Comparator -> Parallel Load register.

    What we need to actually design the truth table and PLA for is the 6 bit counter (this is my best educated guess, at least).

    But at this point I am stuck. I am struggling to visualise how to 'compact' the truth table from 64 terms.

    Obviously the 6 bit counter needs to count from 0-63, but how exactly do you go about optimising the circuit without writing out a 64 line truth table?

    Edit (camjerlams omitted):
    Your answer must include:
    1. A functional description of your design – that is, describe your design in words, diagrams, etc. (10 marks)
    2. A summary of the Boolean function for each Sum‐of‐Product term required in your implementation. This
    may be in the form of a Truth Table or other appropriate Boolean function (5 marks)
    3. A schematic diagram of the Programmable Logic Array implementation. (10 marks)
     
    Last edited: Oct 29, 2013
  8. WBahn

    Moderator

    Mar 31, 2012
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    By considering the functionality that a counter provides.

    Ask yourself the following:

    1) Bit 3 of the counter is presently LO. What conditions need to be met in order for Bit 3 of the counter to go HI on the next clock pulse?

    2) Bit 3 of the counter is presently HI. What conditions need to be met in order for Bit 3 of the counter to go LO on the next clock pulse?
     
  9. uwotm8

    New Member

    Oct 29, 2013
    7
    0
    1) Bits 0 AND 1 AND 2 are HI.
    2) Bits 0 AND 1 AND 2 are HI, at which point bit 4 goes HI and bits 3/2/1/0 go LO.

    That provides a bit of a light bulb moment! Thanks.

    But when bit 4 goes HI, how do you set the lower bits back to LO (since 001111 is followed by 010000). Do you invert the AND and have that fed into the input of the lower order D flip-flops?
    I understand how to implement the 'overflow' of higher bits, what I don't understand is how to implement the 'reset' of lower bits.
     
  10. camjerlams

    Thread Starter Member

    Dec 23, 2012
    56
    1
    For bit 3 to go HI you need bit 1 and 2 to be HI, and same for bit 3 to go low..
     
  11. WBahn

    Moderator

    Mar 31, 2012
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    Assuming you are starting your bit counting with Bit 1 instead of the more conventional Bit 0, that is correct.

    So now, can you design a logic circuit that will implement that objective? Think about how you might reword that sentence to something along the lines of, "When Bit 1 and Bit 2 are HI, we want Bit 3 to ..., otherwise ...."

    At that point, you have an English sentence that almost describes your logic schematic.
     
  12. uwotm8

    New Member

    Oct 29, 2013
    7
    0
    So the zeroth D flip-flop would have an input of /Q from itself (alternates 0-1-0-1-0 etc.)
    The first D flip-flop would take the output of the zeroth flip-flop as its next value
    The second D flip-flop is high when 0 AND 1 are HI.
    The third D flip-flop is high when 0 AND 1 AND 2 are HI.
    and so forth..

    This solves the 'overflow', but how exactly do you reset the lower bits when a higher bit is 'overflowed into'. So when 2 goes HI, 0 and 1 go LO. When 3 goes HI, 0 and 1 and 2 go LO etc.

    I don't understand how to implement this..

    Sigh, this is so over my head. Just let me implement it in a piece of code -.-
     
  13. WBahn

    Moderator

    Mar 31, 2012
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    The logic describe here doesn't match what you describe in the prior post. If the 0th FF is going 0-1-0-1-0 and if the first FF takes the output of the 0th FF as its next value, the it would go x-0-1-0-1.

    Go back to your english description of what the functionality requires.
     
  14. uwotm8

    New Member

    Oct 29, 2013
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    So the same logic applies for each bit above the zero bit.
    The zero bit alternates 0-1-0-1-0 etc.
    If the zeroth bit is HI, the first bit must be HI next cycle.
    If the zeroth bit AND first bit are HI, the second bit must be HI next cycle.
    If the zeroth bit AND first bit AND second bit are HI, the third bit must be HI next cycle.

    But the problem with this logic is, does it not follow this incorrect pattern:

    000000
    000001
    000010
    000011
    000110
    000111
    001110
    etc.?

    The problem being that once a bit is overflowed, the lower bits (excluding zero) need to reset to LO.

    I simply do not understand how I'm supposed to make this count properly. I do not understand how to force the lower bits back to 0 once overflowed (this would solve the problem, wouldn't it?). Could you please open my (non-electronically minded since it's not actually my major) eyes? :confused:
     
  15. WBahn

    Moderator

    Mar 31, 2012
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    Go back to Post #11 and do what it asks. Namely, reword the description you gave just before that into the form I recommended. Let's get that sentence crafted because that will tell you what the implementation needs to be.
     
  16. uwotm8

    New Member

    Oct 29, 2013
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    I believe this is correct:

    "When Bit 1 and Bit 2 are HI, we want Bit 3 to be HI next cycle if it's LO, otherwise we want Bit 3 to be LO"
    (AND Bit 1, Bit 2 and /Bit 3 ?)
     
  17. WBahn

    Moderator

    Mar 31, 2012
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    Okay, we have two people we are dealing with. Basically, uwotm8 hijacked camjerlams thread. Since it is exactly the same problem, it's not a true hijacking like we usually object to, but it does cause confusion because I was assuming that you had made the comment above and now were having trouble converting into a clearer form.

    So read and be sure you understand camjerlams statement and then compare it to yours. You are actually pretty close, just a subtle error that needs to be addressed.
     
  18. uwotm8

    New Member

    Oct 29, 2013
    7
    0
    I only hijacked to lead the thread towards the crux of the question, the 6 bit counter implementation, which I hope has helped camjerlams.

    When bit 1 and 2 (and 0) are Hi invert bit 3, otherwise leave bit 3.

    Which I think would lead to a multiplexer, which is not allowed since its supposed to be implemented on a PLA with and/or gates only.
     
  19. WBahn

    Moderator

    Mar 31, 2012
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    Okay, so what gate can you think of has two inputs and if one input is LO will the output will track the other input but if the first input is HI the output will track in inverse of the other input? The description sounds a lot like a multiplexer, but notice that this gate has a total of two inputs only. Draw a truth table and the answer will jump out at you.
     
  20. uwotm8

    New Member

    Oct 29, 2013
    7
    0
    XOR gate! Which can be implemented using the PLA.

    The only misunderstanding I now have is that we want bit 3 to be changed when bit 0, 1 and 2 are HI (0111 not 0110) and yet you were leading me to only XOR 1 and 2. Where does bit 0 come into play, or am I missing something?

    Perhaps: (Bit 0 AND Bit 1) XOR Bit 2?
     
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