Hi all, I'm a little confused with this circuit. I got this 555 timer PWM circuit from http://www.dprg.org/tutorials/2005-11a/index.html. This webby claims that the output(pin 3) and discharge pin(pin 7) will both enter high and low state at the same time. Below is what it's written on the webby: [In this circuit, the output pin is used to charge and discharge C1, rather than the discharge pin. This is done because the output pin has a "totem pole" configuration. It can source and sink current, while the discharge pin only sinks current. Note that the output and discharge pins go HIGH and LOW at the same time in the oscillator cycle.] However, inside the 555 timer: the FF inside the 555 is connected to the output stage and the NPN transistor. My understanding is, when the condition causes the FF to output a logic 1, pin 3 goes high while pin 7 is shorted to ground because the transistor is turned on. When the condition caused the FF to output a logic 0, pin 3 becomes a current sink meaning logic 0 while pin 7 goes high because pin 7 is connected to +V. Meaning to say that the discharge pin and output pin will always be in opposite logic. Is my understanding wrong? Please do correct me if it is so. Thanks a lot in advance!!