555 timer/logic project assistance needed

Discussion in 'The Projects Forum' started by ds2728, Mar 26, 2013.

  1. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    Hello, I am attempting to build a timer/logic circuit and need some assistance. It has been close to 30 years since I used to do this type of work and now have a need to build something I thought would be simple. I found this forum and thought I might be able to get some assistance here.

    I have attached to pdf documents that attempt to help describe my need. 1 document is a over simplified block diagram, and the 2nd document is a timing chart with 3 eample shown.

    Desription of circuit:

    I have 2 inputs that are fed from a device that uses npn transistors for outputs sinking to zero volts. The output needs to be high whenevr the 2 inputs are active, high. input A will always fire first.

    Safety timer is a timer that will drive the output low in the case that inputs A and B stay high to long. the time on the safety timer needs to be adjustable between 5.-3 seconds

    Skip Timer is an option selection that causes the output to follow the skip timer as long as the inputs A and B are high and the safety timer has not timed out. Skip timer needs to have adjustable high and low times between: .1 - 2 seconds.

    The safety timer and skip timers must always start on the high cycle and be reset whenever the output goes low. This is to ensure that the timers always start from zero.

    I have built a monostable timer for the safety timer, an astable time for the skip timer, a pnp transistor siwtch to convert the npn transistor input.

    I am having a difficult time tying the cuicuit together and receiving the correct response or output.

    Thanks in advance, I am open to any suggestion to this project.

    Thanks, Dave
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    When you say you are "having a difficult time tying the cuicuit together and receiving the correct response or output," could you be a bit more specific? HOW have you tried trying the circuit together and WHAT response ARE you getting?
     
  3. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    I have a monostable timer that is activated with a negative pulse and produces approx. 2 second pulse. I have a pnp transistor to convert the output from my electronic eye with a npn sinking transistor providing me 0 volts when active.

    I am using 12vols dc. When eye is normal condition I have o volts and when active I have 12 volts. So I have a good signal from my eye.

    I have attempted to take the output form 1 eye and the output from the monostable safety timer into an AND gate to produce a signal based on the 2 highs. I have used both an AND gate 14 pin IC (7408, i think), I also attempted building my own AND gate using diode logic.

    I could not get the output from the AND gate to follow the logic of the inputs. I just looked at my bread board and I disassebled that portion of the cicuit. I forget which input was causing the issue, but one of the inputs was not dropping far enough to 0volts and was causing the AND gate to always have a high on one of the inputs. for some reason I want to say the output from the 555 timer was the issue. If I manually tied that input thru a resistor to either 12 volt or 0 volts I could get the output to act coorectly with the elctric eye input as the second input.

    I hope I explained it clear enough for you to understand.

    I also have questions on how/where to tie the 555 timer reset pin into the circuit to get it to reset when the output does go low.

    I think I have a good understanding of what needs to happen, just not enough experience in making it happen.

    thanks, dave
     
  4. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    Hello, I was really hoping someone would be willing to assist me me with circuit design for this application. If anyone can assist in this manner, it would be greatly appreciated. Thanks
     
  5. tracecom

    AAC Fanatic!

    Apr 16, 2010
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    I am trying to understand your block diagram. You have two electronic eyes, which produce a high output when active. You have a transistor inverter on the output of each eye so that the active output is now low. You have the output from the transistor inverters going into the first AND gate, one into input A and one into input B. Is that correct so far?
     
    Last edited: Mar 27, 2013
  6. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    I am sorry for the confusion. the output of the electronic eyes are normally high ( held high with a resistor load ) and when the eye is active it drives the output low.

    My thought was; I needed to invert the output from the eyes, so the input into the AND gate would be correct - high in when the eye is active.

    This is where I used a pnp transistor to invert the signal, this is only due to the fact I had no inverter chip in my supplies. I have since ordered more parts and will have an inverter chip available to me shortly.

    The basic design is as follows:

    1.) During the time that both eyes are active the output needs to be high.

    2.) safety timer starts when output goes high and will force the output low if the eyes stay active longer the the safety timer. my thought is that this would be a monostable timer with adjustable time

    3.) if the skip timer is active, then steps 1 and 2 remain the same with the exception that the output should pulse the same as the skip timer. My thought on this is it would be an astable timer with adjustable high and low times within the cycle.

    4. it is important that both the safety timer and skip timer both start in the high cycle first and is reset when the output goes low.
     
  7. tracecom

    AAC Fanatic!

    Apr 16, 2010
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    OK, I understand what you want. Essentially, you have a four input AND gate.

    And you have a couple of 555's, one configured as a one-shot and one configured as an astable. Are they both working correctly?

    What is not happening that is supposed to happen?

    And I suppose you don't have a schematic, or you would have posted it?

    It may be that all you need is pull down resistors on the inputs to the AND gate that is not functioning properly.
     
  8. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    I do not have the schematic, I do have the AND gate with the oneshot timer built with the 2 eyes. (one step at a time, once I get this working I was going to add the skip timer). I am having trouble with one of the signals not going low enough to drive the input into the AND gate low, hence it appears to always be high. it gores from 12 volts as a high and .7 - .9 volts as a low. until I get back at the project tonight I do not remember which input to my AND gate was causing me troubles.

    Shouldn't I be able to feed the output from the 555 timer directly into the AND gate? I am also feeding a 1k resistor and LED so I can trouble shoot what is going on with my signals, the resistor and LED shouldn't screw with my results should they?
     
  9. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    I will sketch a schematic tonight once I sit down and get to testing again, I will post it tonight. thanks
     
  10. tracecom

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    No, the LED shouldn't cause an issue. First try a pull-down resistor (of about 10k to ground) on the AND input that isn't going to ground. If that doesn't work, put a diode between the output of the 555 (with the anode toward pin 3) and the input to the AND gate. 555's have the ability to sink as well as source current at pin 3.
     
  11. tracecom

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    Apr 16, 2010
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    I breadboarded the attached circuit, and it worked perfectly with no pull-down resistors and no diode between pin 3 of the 555 and pin 6 of the 4081. The LED on pin 4 of the 4081 followed the output of the 555 perfectly. Based on that, I would think you have a wiring error.
     
    Last edited: Mar 27, 2013
  12. elec_mech

    Senior Member

    Nov 12, 2008
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    Here's a shot at a solution. I strongly suggest using a CMOS AND gate, not a TTL version if you're working with 12V from the 'eyes'. You can connect to the inputs directly and save yourself a lot of headache and some parts. The entire circuit operates off 12VDC, so if you're using multiple voltages, this schematic would have to be modified.

    R2 and C1 act as an edge-trigger to the 555 timer. That is, the timer will start when the first eye output goes from low to high. It will ignore the eye until the eye goes from low to high again. This is important because if eye 1 stays high beyond the timer interval, the output of the 555 will remain high. Adding an edge-trigger eliminates this.

    R6 keeps the skip clock off and the astable 555 output low which in turn keeps the NPN transistor open. R4 prevents a short from the output of the AND gate to GND when the skip clock is running. If the skip clock is turned on while the AND gate output is low, the output should remain low. If the clock is on when the output is high, the NPN is opened and closed, causing the output to go low and high. The output may need a large value pull-down resistor if the AND gate does not actively pull the output low.

    I did not include the full 555 circuits - I didn't want to take away all the fun. :rolleyes:

    Also, I'm not sure how you're hooking up the NPN transistor - the connection you've shown doesn't look quite right, but I'd have to see the full schematic first.

    Hope this helps.
     
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  13. tracecom

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    Apr 16, 2010
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    @ds2728

    I completely missed the fact that you are using TTL; I was thinking CMOS the whole way, and my breadboard was built with a CMOS quad AND gate. I know less than nothing about TTL, so just ignore my posts altogether.

    I am sorry to have wasted your time.
     
  14. absf

    Senior Member

    Dec 29, 2010
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    I think you meant 4081 and not 4018. 4018 is a divide by N counter.

    Allen
     
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  15. tracecom

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    You are correct; thanks. I think I have made the corrections on the previous posts.
     
  16. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    OK, here is the first schematic of my inputs. The electronic eyes feeding the inputs are npn transistors that turn on and provide a ground to the inputs on this schematic when the eyes are activated.

    Vcc is 12volts.

    Not shown on the schematic is an LED thru a 1k resistor to ground hooked up to the AND gate output pin 8

    Inputs to the AND gate are approx. .97 volts and the LED is off. If I activate either eye the input for the respective eye goes to 12 volts. and the LED turns on.

    So my LED is turning on with only one eye being activated.

    I tested the AND gate by tying the inputs directly to Vcc thru a 10k resistor, and then grounding them and the inputs and output work correctly.

    Thanks in advance for assistance. If there is a better idea to invert my inputs from the electronic eyes, I am open to any suggestions and/or changes.
     
  17. tracecom

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    I said I don't know anything about TTL, but are you running it at 12V?
     
  18. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    elec_mech, This looks like you hit a homerun. what is the IC# for the cmos AND gate? I have also uploaded a schematic of my input circuit. basically the electronic eye has an npn output transistor, where the emitter goes directly to ground and the collector is what to fed to to outside world. So the collector of the npn transistor is what would be feeding the inputs to the circuit. my schematic is an attempt to invert the signal to use with an AND gate logic.

    On your design, to assure that the safety timer u1 signal starts when the output of cmos AND gate goes high, could r1 be connected to input 2 so that the safety timer starts when the second input goes high. And to assure that the safety timer is reset an starts at zero time everytime, could the reset pin 4 on u1 be tied to input 1, this way input 1 will rest the timer and when it goes high it will assure the timer will start at zero time?

    Input 1 always goes high first and then input 2, then input 1 will always go low first then input 2 will follow.
     
  19. ds2728

    Thread Starter New Member

    Mar 26, 2013
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    elec_mech, here is my input schematic showing the npn transistors in the electronic eyes, and my attempt to invert the signals for the eyes to feed the AND gate
     
  20. elec_mech

    Senior Member

    Nov 12, 2008
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    Hmm, looking at your schematic, you have a 10kΩ pull-up and a 10kΩ base resistor - these are going to act as a voltage divider which could lead to problems. I'd suggest making the base resistor 1kΩ or less.

    TTL ICs operate off of 5VDC only, give or take half a volt. I'm not sure what voltage you are powering the 7408 or transistors with.

    But let's see if we can simplify this a bit.

    Instead of an AND gate, let's use an NOR gate which will output a high signal only when all of the inputs are low. This will eliminate the need for the transisitors acting as inverters.

    We can use a 3-input CMOS NOR gate such as the CD4000.

    Now, the 555 outputs a high signal, so it will need to be inverted. Conveniently, the CD4000 has an inverter gate as well, so we'll use that instead.

    Because the eyes are open collectors and the output is left floating when the eyes are 'off', we need to add pull-up resistors, R1 and R2.

    Since the 555 timer is triggered with a low signal, we can eliminate the transistor from earlier.

    C2 is added to help eliminate noise generated by CMOS ICs that can affect the rest of the circuit. On the same subject, each 555 should have a 1uF electrolytic and a 0.1uF ceramic or Mylar cap - both across Vcc and GND - to eliminate noise generated by each 555 as well.

    VDC can be anything from 3-15VDC, but I would strongly suggest using the same 12VDC source powering the eyes. This will eliminate a lot of troubleshooting.
     
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