PIC10F320 with specific reference to Numerically Controlled Oscillator.

Compare this to a 555 plus external resistors and caps.

 

You can make a 50% duty oscillator with a CMOS 555 timer and 3 parts, all you need for the oscillator is the timing cap, and a one resistor from pin 3 back to the cap. The other part is the filter cap on pin 5.

 

As noted previously, this approach will only be 50% if the output actually straddles the active range, which it may or may not, and if the output impedance is the same for both a high output and a low output, unless this is kept to a negligible fraction of the external. It is also dependent on the specifics of the load due to the very finite drive capability of the output.

I don't recall the OP givning any kind of specs on how close to 50% the duty cycle needs to be. I only recall the initial (or an early) post indicating that 48% wasn't good enough.

 

The CMOS 555 (I mentioned) would get very close to 50% and tolerates light output loading without too much trouble because its output drivers pull very close to the rails.

A slight + or - bias can be added with a 1M pot between 5v and GND and the wiper going to the osc cap.

The problems with the OP's original circuit in post 1 is that it is a standard astable using the discharge pin, so the pin3 osc circuit I mentioned will do a lot better, and is simpler than the typical "duty cycle astable" that needs added diodes.

 

Agreed.

However, I got the impression from several things the OP said that he didn't want to have any pots or other adjustments in there. That's why I think he will be better served by an AMV running at twice the frequency followed by a frequency divider. He can focus his component selection on achieving the desired frequency without worrying about duty cycle, doesn't have to worry about loading effects or driver imbalance, and is guaranteed to have 50% duty cycle to the degree that the oscillator frequency is stable.

 

Agreed.

However, I got the impression from several things the OP said that he didn't want to have any pots or other adjustments in there. That's why I think he will be better served by an AMV running at twice the frequency followed by a frequency divider. He can focus his component selection on achieving the desired frequency without worrying about duty cycle, doesn't have to worry about loading effects or driver imbalance, and is guaranteed to have 50% duty cycle to the degree that the oscillator frequency is stable.

And, to the degree that clock-to-Q delays are identical for rising and falling outputs.
I agree, though, that a toggle FF should get you closer without tweaks, and may be more stable, than the 555 with pin 3 fed to the cap through the timing resistor.

 

thank you all for your answers
I think that the problem is more difficult than i thought it to be so i will re-post the specs:

1) Frequency modulator for capacitive sensor (timing cap in initial post)
2) Ultra Low power (< mA @ 2V)
3) Capacitive sensor limits the oscillating frequency to 100Khz
4) Capacitive sensor has a range of 300pF - 350pF
5) I want to utilize multiple such oscillators as semipassive RFIDs in order to have frequency division multiplexing (FDMA) scheme (long story).
6) 50% duty cycle is important because otherwise i have even harmonic energy <> 0 (smaller bandwidth)
7) The F(Csense) should be linear if possible in order to ease calibration (correct me if i'm wrong)
8) Calibration should be avoided using pots and other user-controlled modules because once on the field, the sensors will be unreachable. Preferably one initial calibration and followingly, software calibration is an option.
9) Accuracy is not a critical factor +-5-6% can be compensated.


(I can nearly see the dead end)

 

You've added some things that complicate matters (I think).

Frequency will not be linear with respect to capacitance. As noted by others, the period will be linear and so the frequency will be recipricol.

When you say accuracy is not important, accuracy of what? Frequency? Duty cycle?

If 50% duty cycle is important and it is important that it stay that way over varying conditions without adjustment, then I would definitely recommend using the frequency divider.

 

You've added some things that complicate matters (I think).

Frequency will not be linear with respect to capacitance. As noted by others, the period will be linear and so the frequency will be recipricol.

When you say accuracy is not important, accuracy of what? Frequency? Duty cycle?

If 50% duty cycle is important and it is important that it stay that way over varying conditions without adjustment, then I would definitely recommend using the frequency divider.

Initially i thought that by describing only the 555 part someone would come up with an answer but i think that this is a more complex problem.. Anyway, if my last post was out of subject i will repost it in a new thread.

50% duty cycle is important, but given the fact that the capacitor has a freq limit of 100khz the usage of a divider, further limits my bandwidth.

Accuracy of humidity measurement is not a critical factor. I calculate accuracy by finding the output frequency, then

F = 1/(Csense*(R1+2R2)*ln(2))
Csense = 1/(F(R1+2R2) * ln(2))

Csense known -> %RH known.

I know i added a lot of stuff to the equation but i didnt want to confuse people so i posted a subset of the problem..

 

A 50% duty cycle square wave does not eliminate harmonics. It only eliminates even harmonics. Your first harmonic will be at 3 times the fundamental instead of 2 times, but the total harmonic energy is really a function of rise and fall times more that it is a function of duty cycle.

 

A 50% duty cycle square wave does not eliminate harmonics. It only eliminates even harmonics. Your first harmonic will be at 3 times the fundamental instead of 2 times, but the total harmonic energy is really a function of rise and fall times more that it is a function of duty cycle.

I already mentioned that:

6) 50% duty cycle is important because otherwise i have even harmonic energy <> 0 (smaller bandwidth)