Hi

I am currently searching for an resonant circuit to act as a signal conditioner for a capacitive humidity sensor. For starters i started playing with the all time favorite 555 timer (specifically the cmos intersil 7555 ) in astable mode. However one of the requirements of my project is 50% duty cycle output square pulses. I used the circuit with the single resistor in order to achieve that and apart from the fact that i didn't get exactly 50% duty cycle (48%), stray capacitances of other circuits connected in the output resulted in a change of frequency, thus errors in my measurement.

Getting to the point: i understand that the basic circuit for astable operation of the 555 requires 2 resistors (R1,R2) and a capacitor. The capacitor charges through R1,R2, discharges through R1 and the threshold and trigger pins manage the output based on the capacitor voltage. My first thought after understanding this was why couldn't we make our lives simpler by connecting a resistor right after discharge pin and get a high output calculated by ln(2)R1C and low by ln(2)R2C. Intuitively, by setting R1=R2=R i can get a 50% duty cycle without adding circuitry to the output. Anyway, i build the attached () circuit but the result was a failure. It cannot produce any pulses at all

My questions:
1) What is wrong with the attached circuit? (which seems allright to me)
2) Can anyone propose a low power (<1mA@2V or less) signal conditioner for capacitive sensors with frequency output (preferably above 20-30Khz)?

Thank you in advance
Lefteris

 

What humidity sensor are you using?

 

Anyway, i build the attached (View attachment 53815) circuit but the result was a failure. It cannot produce any pulses at all

If the Discharge pin is at 0V, what voltage will the capacitor settle to? Hint: Think "voltage divider".

If you need a 50% duty cycle signal then just take the output of a non-50% duty cycle signal at twice the desired frequency and use it to clock a flip-flop. This will also provide a lot of isolation between the timing components and any stray parasitics that would affect them.

 

Here is the standard 50% duty cycle 555 astable.

I still would like to know what kind of humidity sensor you are using. Is it the Humirel HS1101?

 

The ideal situation of the 555 circuit is 50%/50%, but real world is not like that, you may using 9.1K to replace R2(10K) and in series with a 2K pot, and then you can adjust the value of the 2K pot to reach to 50%/50%.

 

In your original schematic, your timing cap will charge to roughly 2/3 of Vcc when the threshold voltage is exceeded, causing pin 7 (discharge) to be turned on. When pin 7 turns on, you basically wind up with a voltage divider with 50% of the resistance to ground and 50% of the resistance to Vcc from their junction with the timing cap, so your eventual voltage will be roughly Vcc/2 or ~2.5v. The trigger voltage value is roughly (threshold voltage / 2), which as you have things wired, will always be ~1/3 of Vcc, or ~1.667v. Since the timing cap voltage will always be higher than the trigger value, your timer output will never change states.

Try charging/discharging the timing cap via a resistor from the output pin (#3) instead, maintaining connections from the timing cap to trigger (#2) and threshold (#6) inputs. Keep the reset (#4) pin tied to +V.
220pF for C1 and 100k for R1 should give you around 30kHz out.

 

@ Tracecom

What humidity sensor are you using?

HCH1000 from honeywell
Your proposed schematic includes a diode that inserts extra inaccuracies and complexity to my measurements. I have considered (and tested) this schematic but i will try to avoid it

If the Discharge pin is at 0V, what voltage will the capacitor settle to? Hint: Think "voltage divider".

If you need a 50% duty cycle signal then just take the output of a non-50% duty cycle signal at twice the desired frequency and use it to clock a flip-flop. This will also provide a lot of isolation between the timing components and any stray parasitics that would affect them.

I have also considered (and tested) the flip flop solution but for the above reasons (plus the current consumption) i will try to avoid it.

Try charging/discharging the timing cap via a resistor from the output pin (#3) instead, maintaining connections from the timing cap to trigger (#2) and threshold (#6) inputs. Keep the reset (#4) pin tied to +V.
220pF for C1 and 100k for R1 should give you around 30kHz out.

After the 555 circuit, comes a AT32033 transistor. This transistor inserts some stray impedance and as a result, some inaccuracy. I tried to decouple it with a series capacitor but after the capacitor i got negative voltage and didnt continue using it with the transistor as i feared of destroying it (didn't check the transistor manual yet). However, could you draw a schematic of what you propose so as to better understand what you mean?

The ideal situation of the 555 circuit is 50%/50%, but real world is not like that, you may using 9.1K to replace R2(10K) and in series with a 2K pot, and then you can adjust the value of the 2K pot to reach to 50%/50%.

I also try to avoid pots :/.Morever i think that whatever i do, with the basic astable circuitry i cannot achieve 50% as
Th = (R1+R2)Cln(2)
Tl = R1Cln(2)
(correct me if i'm wrong)

In order for Th=Tl => R1 = 0..



Thank you all in advance

P.S what about other signal conditioners for cap sensors?

 

I don't understand the objection to using the flip flop approach. You say "for above reasons", but the "above reasons" refer to diodes causing inaccuracies and complexities. There are no diodes in the flop flop approach. At 30kHz, the flip flop will consume next to nothing and this approach is going to give you as close to a 50% duty cycle, which seems inportant, as any other approach you might try. What will go up is the current consumption of the 555 circuit, since it is running at 60kHz, but that can almost certainly be minimized and probably brought below what you are currently experiencing, by proper choice of timing elements.

 

Try charging/discharging the timing cap via a resistor from the output pin (#3) instead, maintaining connections from the timing cap to trigger (#2) and threshold (#6) inputs. Keep the reset (#4) pin tied to +V.
220pF for C1 and 100k for R1 should give you around 30kHz out.

This appears to be the best solution if you are using the 7555 which is cmos. You could insert a buffer between the 7555 output and the next stage.

Please note that manufacturing tolerances result in inaccuracies of the 1/3 and 2/3 thresholds and some trimming of the control voltage with a resistor may be necessary to achieve the desired accuracy.

Timescope.

 

This appears to be the best solution if you are using the 7555 which is cmos. You could insert a buffer between the 7555 output and the next stage.

By inserting a buffer wouldn't i greatly increase the power consumption?

Please note that manufacturing tolerances result in inaccuracies of the 1/3 and 2/3 thresholds and some trimming of the control voltage with a resistor may be necessary to achieve the desired accuracy.

Do you suggest that i should set the control voltage my self, instead of connecting it with a cap to V+ in order to increase accuracy?

I don't understand the objection to using the flip flop approach. You say "for above reasons", but the "above reasons" refer to diodes causing inaccuracies and complexities. There are no diodes in the flop flop approach. At 30kHz, the flip flop will consume next to nothing and this approach is going to give you as close to a 50% duty cycle, which seems inportant, as any other approach you might try. What will go up is the current consumption of the 555 circuit, since it is running at 60kHz, but that can almost certainly be minimized and probably brought below what you are currently experiencing, by proper choice of timing elements.

I tried to avoid adding new components in order to keep power at low levels. However it seems that i have not searched for low power flip flops. I found this :
http://www.ti.com/lit/ds/symlink/sn74lvc1g175.pdf
Which is a fitting d-ff for my project (low power). Therefore, i will use the flip flop approach together with the default astable circuitry.

 

By inserting a buffer wouldn't i greatly increase the power consumption?

An unused cmos gate could be used as a buffer to isolate the 7555.

Do you suggest that i should set the control voltage my self, instead of connecting it with a cap to V+ in order to increase accuracy?

You can make small adjustments to the pulse width by connecting a suitable resistor from pin 5 to V+ or ground.

Pin 5 can be used for pulse width modulation.

Timescope.

 

If you care about the power dissipation, then you can using 74HC14 to generate square wave, and you can adjust the pot to get the right value of resistors(50%/50%), and using fixed resistors to replace the pot.

If you want to know more about the calculation formular of frequency, the n you can check the fig 14 from the 74HC14 datasheet.

 

An unused cmos gate could be used as a buffer to isolate the 7555.

You can make small adjustments to the pulse width by connecting a suitable resistor from pin 5 to V+ or ground.

Pin 5 can be used for pulse width modulation.

Timescope.

1)nice idea for the isolation. However, what do you mean by "unused"?
2)Is there any expression that describes the pulse width as a function of V in pin 5?

 

Use this circuit method for 50% duty cycle

 

Use this circuit method for 50% duty cycle

There are a few problems with this approach. First, the 50% duty cycle relies on the output going rail-to-rail, or at least being symmtric about the control points.

Second, the timing (both the frequency and the asymmetriry) are load dependent due to the finite output impedance and drive capabilities of the 555.

 

If you care about the power dissipation, then you can using 74HC14 to generate square wave, and you can adjust the pot to get the right value of resistors(50%/50%), and using fixed resistors to replace the pot.

If you want to know more about the calculation formular of frequency, the n you can check the fig 14 from the 74HC14 datasheet.

Thanks for the suggestion, i will experiment with this later on. However, the power consumption of the IC is at 50mA, which is a lot higher than the 7555 IC. I will however experiment with astable multivibrators using schmitt triggers. Also, are you aware of any circuit that has a linear frequency response to capacitance (preferably low power)?

 

Any RC oscillator. You can make one with a CMOS schmidt trigger inverter like a 74HC14, and just one resistor and one cap. Google for "CMOS inverter RC oscillator".

 

Thanks for the suggestion, i will experiment with this later on. However, the power consumption of the IC is at 50mA, which is a lot higher than the 7555 IC. I will however experiment with astable multivibrators using schmitt triggers. Also, are you aware of any circuit that has a linear frequency response to capacitance (preferably low power)?

The CD4060 that you can using crystal or rc to generate the square wave.
You can find the application circuit on page 4.

 

In most RC oscillators, the period is linearly proportional to capacitance. The frequency will therefore be inversely proportional to capacitance. A graph of frequency vs capacitance will not be a straight line. It will be a hyperbola.

 

If you still want to using NE555 to be the 50%/50% oscillator, your circuit is different from the standard NE555 circuit, so it could be there is no oscillation or the duty cycle not as you want, you can using the circuit as below and R3 set to 9.1K, if you can find a 9K that is match to your 10K.