I was getting curious in class and drew the following circuit. Is there a reason this circuit won't work as an AND gate? (if it does, it uses 1 less transistor than the standard AND gate!) The main issue I could see is that it draws current from A when it is on, but wouldn't that be fine in some circumstances?

 

For a single gate it might not be such a big deal. What happens if 1 million gates on a single die draw power from A? How about 10 million? How about 100 million? The big advantage of CMOS gates is that they draw almost no quiescent power when they are not switching.

 

But you need transistors to generate the /B signal from the B signal.

 

But you need transistors to generate the /B signal from the B signal.

My circuit is a little misleading: 3 shown in the picture and 2 implied for the inverter is 5 total. It would be 3 assuming complemented inputs are available.