4017 counter woes

Discussion in 'The Projects Forum' started by Otaku, Dec 15, 2010.

  1. Otaku

    Thread Starter Active Member

    Nov 19, 2008
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    Hi all,
    Since I have a good working solution for my LED latching issue (2N5060 SCR's), I decided to start another thread to see if there's a solution to the latest issue with the test system I'm designing. Thanks to all who advised on that solution.
    Still have one problem that I thought would be resolved by using transistors nstead of relays for switching from one test channel to another. I keep getting false positives when running tests, due to the transistor (2N2222) staying high past the point where the 4017 counter increments to the next output pin. It's only about a millisecond or so, but that's enough to cause the AND gate (which receives the clocked output signal from the 4017 and the test result -a voltage - to each channel inputs) to go high when it shouldn't. So here's my question. Is there a way to slightly delay the output from the pins of a 4017? By this I mean, when the counter increments to it's next output somehow hold that pin low for a short, controlled time. I'd only need to be able to keep the pin low for 0.5 sec max. This would allow the 2N2222 to shut off and not cause a false trigger. If this is not possible to do, is there a counter device, similar to the 4017, that has the capability to follow the high/low intervals of a 555 oscillator, unlike the 4017 that switches on the full clock period (high + low)? The output sequence would be 555 = high, Q1 = high, 555 = low, Q1 = low, 555 = high, Q2 = high and so on.
    Ideally, this device would be able to incremetally switch a signal input that independent of the supply voltage i.e. no signal input = no output on the active pin. Hopfully such a device exists; this effect could probably be built using a mess of different logic gates, but I'd like to avoid getting overly complex, if possible.
    Apologies for the lengthy post. As always, all help is greatly appreciated.
     
  2. Wendy

    Moderator

    Mar 24, 2008
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    What is the schematic of what you're having trouble with. I have some ideas on the subject, but I want to see what your doing first.
     
  3. Bernard

    AAC Fanatic!

    Aug 7, 2008
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    Are you using just one LM 339 whos output is fed to 12 AND gates? If so add one more AND between LM & 4081 buss line. Input 1 is LM, 2 is clock; the negative part of the clock, 100 to 500 ms.will blank out the trailing edge of the 4017 pulses.
     
  4. Bernard

    AAC Fanatic!

    Aug 7, 2008
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    If last post works it creates another problem with first failure alarm which may be fixed by feeding clock to two sascaded 555 one shots. Output of first is strobe pulse for failed test, snd for blanking pulse to added AND.
     
  5. Otaku

    Thread Starter Active Member

    Nov 19, 2008
    128
    2

    Bill, here's a drawing of the circuit that is giving me the grief. The 4081 receives two inputs to each gate, one from the 4017 (A inputs) and the return signal from the electrode that is being tested. The test for the electrodes is continuity only; if the connection is good, a 12VDC signal goes to the 4081 gate at the same time as the 4017 signal, triggering a SCR and lighting a LED. The problem is that the 2N2222's are not turning off in time to prevent crosstalk between gates on the 4081, resulting in a false positive on the next gate. The overlap is ~1 ms, but that's a lifetime to a CMOS device.
    The second drawing is of the 4081-SCR-LED board. This shows the portion of the circuit receiving the clocked 4017 and 12VDC return signals into the 4081 and the outputs to the SCR's and LED's.
    I know these are not real schematics, but they are accurate.

    Edit - Ooops! Maybe not as accurate as I thought. I spotted a couple of mistakes - I'll fix them and re-post the drawings in the morning.
     
    Last edited: Dec 16, 2010
  6. Bernard

    AAC Fanatic!

    Aug 7, 2008
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    After checking your drawing, this might be better: Add a AND between common emitter OR gate & 4081 buss input line. The inverted clock provides a strobe pulse after all signals have settled down.
     
  7. Otaku

    Thread Starter Active Member

    Nov 19, 2008
    128
    2
    Hey Bernard,
    That looks interesting. I don't have an OR gate in the circuit (as far as I know LOL). The 4081 buss input line and the clock signal from the 4017 are going into a 4081 AND gate. What is the device that you show receiving the Clock signal and going to the AND gate?
    I'm not sure what's going on past the AND gate output. Are the outputs of all the AND gates combined into a common buss? If so, that presents a problem as each test result has to be sent (or not sent, in the event of a failure) to a specific SCR/LED combo.
     
  8. Bernard

    AAC Fanatic!

    Aug 7, 2008
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    The triangle represents a buffer, or amplifer, or with added circle on apex is then an inverting amplifier like a 4049. The 4081 AND output goes to all B " inputs" of 12 4081's, which are already tied together per your drawing,so no change in operation.A inputs still come from 4017 outputs. All 12 outputs still go to respective SCR's. I would add a pull down resistor, 10k, from 2N2222's emitters to ground.
     
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