4 bit up/down counter project using D flip flops

Discussion in 'Homework Help' started by BruceBruce, May 18, 2011.

  1. BruceBruce

    BruceBruce Thread Starter New Member

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    I'm trying to design and test a 4-bit version of an Up/Down Counter using D Flip flops. I need it to be Up'/Down = 0 then the circuit should behave as an up counter. If Up'/Down = 1 then the circuit should behave as a down counter. I also need to create an input waveform file to test the procedure in a "full count" up and down.

    Oh i need to design this in Quartus II software. It can be a schematic or VHDL code.

    Thanks for the help hopefully.
  2. Georacer

    Georacer Moderator Staff Member

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  3. BruceBruce

    BruceBruce Thread Starter New Member

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    Thats an up/down counter using a jk flips flops. i need it with d flip flops. I can write the code for a Four bit counter with d flip flops but i dont know how to make it an up and down counter.
  4. BruceBruce

    BruceBruce Thread Starter New Member

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    would i design it similarly to that with the d flip flops instead of the jk flip flops and have the OR gates going into the D input instead of the J and K inputs. How would the first D input go? (pictures help lol im good with those)
  5. BruceBruce

    BruceBruce Thread Starter New Member

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    this is what i got so far:
    [​IMG]

    Uploaded with ImageShack.us

    well i dont know what to plug into the d input of the first FLip flop. In the diagram for the JK flip flop 4 bit counter it had Vdd as the first input to j and k. What is Vdd and how do i incorporate that into my diagram. Also the "up/down" is that just a regular input labeled up/down? i know the q0-q3 are all the outputs but where do i end that last "NOT Q" to?

    Hopefully you guys can answer this and help me fix the drawing. I got tell friday at midnight to turn it in for a grade. Ill owe whoever helps me out big time. If you would like to email me than please send it to <SNIP>. Thank you.
    Last edited by a moderator: May 20, 2011
  6. Georacer

    Georacer Moderator Staff Member

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    I haven't been on a computer in the last 48 hours, hence the late reply.

    Let's think about the difference between a JK FF and a D FF and how we can convert the second into the first, to serve our purpose.

    In the schematic I posted you, you will notice that a signal coming from an OR gate drives both J and K inputs of a JK FF, flipping its state each time it has a value of '1'. The D FF doesn't have that functionality inherently. We must build some circuitry to produce it.
    Remember: On the presence of a '1', we want the FF to switch state. What if we take the Q' output of the FF and AND it through a gate along with the '1' signal? Do you see how that would work?

    You can find another proposition in this thread:
    http://forum.allaboutcircuits.com/showthread.php?t=45624
  7. BruceBruce

    BruceBruce Thread Starter New Member

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    Also in the quartus program how do i get "Q NOT"? there isnt a pin for it on the D Flip Flop icon. do i just run a Not gate off the Q? i attached a pic of it

    Attached Files:

  8. BruceBruce

    BruceBruce Thread Starter New Member

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    heres the new design. let me know what you think. I gotta turn this in by midnight tonight(california time PST) GeoRacer.

    Attached Files:

  9. Georacer

    Georacer Moderator Staff Member

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    That not quite right. Since you seem to not handle a new schematic well, why don't you take the AAC schematic as it is and replace the JK FF, with a module that will be comprised of a D FF, and an AND gate.

    You have the J/K common input of you module which should switch state when the signal from the OR gate on the schematic is '1'.
    In other words, you need to find a way to give the D FF input a Q when the OR output is '0', and Q' when the OR output is '1'.
    That can be accomplished with a 2-to-1 MUX.

    Can you figure out how?

    The first FF will have its hypothetical OR input raised to '1' permanently (or just connected to its Q' for economy).
  10. Bill_Marsden

    Bill_Marsden Moderator Staff Member

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    What are these? I haven't run into those logic symbols before,

    [​IMG]

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  11. BruceBruce

    BruceBruce Thread Starter New Member

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    at the moment. No
  12. mannycc

    mannycc New Member

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    Hi, figured out circuit for DFF (asynchronious) counter will post if interested?
    Rgds.
  13. MrCarlos

    MrCarlos Member

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    Hola BruceBruce

    As for your messages I Know the D Flip-Flop in Your Quartus II Has not Q’ . So you need Add a NOT Gate which it’s input goes to Q on the D FF. this way you have the Q’ on the NOT gate output.

    Take a look the images attached and keep in mind the sentences there.
    This will help you next time.
    saludos
    a sus ordenes

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  14. BruceBruce

    BruceBruce Thread Starter New Member

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    Yes please post it. I just did one more redo with georacers advice.
  15. BruceBruce

    BruceBruce Thread Starter New Member

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    That is similar to what i had but i used a 2-1 mut like suggested earlier
    which is the same as the two and gates and the or.
  16. mannycc

    mannycc New Member

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    Here it goes.
    If your program doesnt have Q' you may also tap a not gate on Q output.
    The DFF Q' output is connected to D input to function just like JKFF. The circuit is simulated and working fine and you may also include set/reset function. Hopefully can help.

    Attached Files:

  17. BruceBruce

    BruceBruce Thread Starter New Member

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    but i had switched the AND gates on your design with OR gates and your OR gate was an AND gate. As you guys can see im not very good with this stuff and now all my designs are mixing up.
  18. Georacer

    Georacer Moderator Staff Member

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    @ Bill
    This is a Multiplexer or MUX in short. This one is a 2-to-1 one with 1 control bit.

    @BruceBruce
    I tried to help you find the solution on your own, but the thread is now cluttered and I doubt you will end anywhere now. It's probably late for your deadline now, but knowledge is never wasted.

    There are many ways to answer your question. manycc in post #16 gave a legit answer of an asynchronous counter. While the circuit is operational it has some foundational differences with the synchronous counter of the AAC e-book and I prefer it.

    Call me lazy but I generally don't like to re-invent the wheel and prefer to modify ready solutions, that's why I told you to simulate the T FF (a JK FF with its input pins shorted) with a D FF. This is what I 'm posting below too. Replace it in your schematic and you 're good to go.
    It is not the best or most economic solution, but it's a fast and easy one.
    [​IMG]

    Attached Files:

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