Thanks! I was kicking myself when I saw the very minute error on the assignment. After prolonged lack of sleep while staring at 0's and 1's they seem to all start blurring together into a long blob.

I think that's called the "Singularity"

 

How many inverters can you put on a single line?

Lots, but it's easier to store something in a FF and pull it from a different clock if you need to delay the data.

Download the Xilinx ISE, it's free development environment with simulation/synthesis for the lower end (hobby affordable ish) chips, you need to pay if designing for an FPGA capable of becoming a 10Gbit Network router or switch, for example. I'd like to get an AAC Soft Processor going that works in both iVerilog Simulation and can be synthesized on Xilinx.

 

Lots, but it's easier to store something in a FF and pull it from a different clock if you need to delay the data.

Download the Xilinx ISE, it's free development environment with simulation/synthesis for the lower end (hobby affordable ish) chips, you need to pay if designing for an FPGA capable of becoming a 10Gbit Network router or switch, for example. I'd like to get an AAC Soft Processor going that works in both iVerilog Simulation and can be synthesized on Xilinx.

It's not meant to be a delay, I'm saying that the maximum is, theoretically ∞, invert, then invert, then invert, then invert, then....

I think what you meant was compare the non-minimized version to the minimized version, right?

 

It's not meant to be a delay, I'm saying that the maximum is, theoretically ∞, invert, then invert, then invert, then invert, then....

I think what you meant was compare the non-minimized version to the minimized version, right?

The maximum allowed components he was allowed to use for this assignment vs. the version he made that had left over options.

 

The maximum allowed components he was allowed to use for this assignment vs. the version he made that had left over options.

I think we've each made a mistake here....

I thought this was another thread regarding truth tables I've also been a part of...

I think that when the OP said,

There were more parts to the assignment that I left out

you thought he meant leftover parts for the SSD decoder...

 

Yeah, I got the threads mixed up too. I hate it when that happens.

 

Now I'm thoroughly confused!

 

Now I'm thoroughly confused!

Yeah, we all are.... we were making points about a topic neither of us was on the same page on, but worse, it wasn't this thread...