4 bit synchronous dff counter that resets at 5

Discussion in 'Homework Help' started by FootsyPJs, Apr 11, 2013.

  1. FootsyPJs

    Thread Starter New Member

    Apr 11, 2013
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    Hey everyone,
    I need a little help with this problem. I am supposed to design and code (in pure structural verilog) a synchronous 4 bit counter that is triggered on positive clock edges and that resets back to 0 when the counter reaches 5. Any help in understanding this would be appreciated. Especially the what goes where, I am unclear on how the dff increments when there aren't any inputs, I'm assuming that the input is a pure logic 1. However, how does it recognize when I have reached 5 or any other number for that fact and know to enable the reset?
     
    Last edited: Apr 11, 2013
  2. tshuck

    Well-Known Member

    Oct 18, 2012
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    675
    It just so happens that I recently wrote some articles for the ebook, regarding synchronous counters and modulus counters. They are still under review(I guess) and you can see the thread for Synchronous Counters and, the one that is probably geared toward your problem, the Modulus Counter.

    Hope this helps!
     
  3. FootsyPJs

    Thread Starter New Member

    Apr 11, 2013
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    0
    It helps a ton! Thank you very much!
     
  4. FootsyPJs

    Thread Starter New Member

    Apr 11, 2013
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    Would anyone know how to represent the output for a DFF?
     
  5. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    I'm not sure I follow. The output of the flip-flop(Q) is part of your 4-bit count.

    Represent it how?
     
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