if i have 4-bit shift register needed to
- 7 clock pulses to store and to read the data register (2*4 -1)
- 8 clock pulse to clear the data register (2*4 )

Is it the correct or Not?

 

Why would you ever need more than four clock cycles to do anything?

It's not completely clear what you mean by your question. Walk through your reasoning for your answers and we will probably figure out both exactly what you are trying to do and whether or not you are correct in your reasoning.

 

I was thinking that for a 4-bit shift register we would need 4 clock pulses to store and then 4 clock pulses to get them out, but it turns out that 4 pulses to store and 3 pulses to get all output.
I tried with Verilog code as well as Xilinx Schematic using D-FF and got the same result. Is this correct (7 pulses instead of 8)?

 

You are still making us guess at what you are trying to do. No it sounds like you are talking reading the data only at the final stage and not in parallel. In that case, yes, you need seven and not eight because after the fourth not only is the last bit loaded in but the first bit is available at the output.