4-bit ring counter only using D Flip-Flops

Discussion in 'Homework Help' started by mikez, Jan 31, 2013.

  1. mikez

    Thread Starter Member

    Jan 21, 2013
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    Hi there,
    I need to construct a 4-bit ring counter only using D Flip-Flops and a few necessary gates to come up with the output that I am looking for.

    I am setting up the circuit to be run on an FPGA which has a global reset switch that is already set up so I do not need to worry about a clear. The output thats I will be looking at are: 0001, 0010, 0100, 1000. I have an idea of how the ring counter works and how it passes a value through - my problem lies in how I only get a single "1" to pass through. From my reading I know that for a ring counter to work the first flip-flop in the chain must have a 1 passed to it.

    Code ( (Unknown Language)):
    1.  
    2. A   B   C   D
    3. 1   0   0    0
    4. 0   1   0    0
    5. 0   0   1    0
    6. 0   0   0    1
    7. 1   0   0    0
    8.  
    9. etc.
    10.  
    If I connect the Vcc and an OR gate to my first flip-flop that will give me a "1" and will start the chain, but the problem is that no matter what I will constantly be pushing 1's through my chain of flip-flops and I will never reach the outputs that I need to read in. Any suggestion or advice on how to remedy this problem?
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    In some FPGAs you can specify whether a FF gets set LO or set HI on a global reset.

    Let's assume you don't have that. Heck, let's assume your FFs don't have a reset input of any kind. So make a table of what signal you want going to the D input of each FF depending on whether your RESET signal is HI or LO.
     
  3. mikez

    Thread Starter Member

    Jan 21, 2013
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    0
    Hmm...I am a bit confused by your response. The D FF's that I am using have no preset port on them. Only inputs I have to work with are the CLK and D. I have a truth table written up for what I want to accomplish:

    Code ( (Unknown Language)):
    1.  
    2.  
    3. Normal        Next State            Flip-Flop Output
    4. A  B  C  D    A+  B+   C+  D+    D(A)   D(B)    D(C)       D(D)
    5. 0  0  0  0    x    x   x    x    x        x       x         x
    6. 0  0  0  1    0    0   0    1    0        0       0         1
    7. 0  0  1  0    0    0   1    0    0        0       1         0
    8. 0  0  1  1    x    x   x    x    x        x       x         x
    9. 0  1  0  0    0    1   0    0    0        1       0         0
    10. 0  1  0  1    x    x   x    x    x        x       x         x
    11. 0  1  1  0    x    x   x    x    x        x       x         x
    12. 0  1  1  1    x    x   x    x    x        x       x         x
    13. 1  0  0  0    1    0   0    0    1        0       0         0
    14.  
    I wish there was an easier way of inputing these truth tables! :mad:

    If I were to have a HI coming into my first FF and to keep it a one I would OR it with my final flip flip so the D(A) = 1 + Q(D). The problem is is that I will always be getting the one going through my flip flops. I spoke to someone today and they had said that I would need to put in an inverter to give me the 0's in there and to space out the 1. The problem is where do I place the inverter? I will always be getting a 1 going into my first flip-flop because of it being connected to the HI connection. I can't put the inverter after the OR gate going into my first D port on my first flip-flop.

    I am just perplexed on what to do with the constraints I am given and I don't think its possible to have this work without having some sort of input come in.
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    Note that I said SOME FPGA's had this ability. I never claimed that ALL do. So your's doesn't. Fine. So the case that I said to consider is a perfect match for your situation. Sounds great.

    Are you sure about this table. It looks to me like this table is saying that you don't want anything to change at all. For instance, when

    S = {A,B,C,D} = 0001

    you are saying that the next state to be

    S+ = {A+,B+,C+,D+} = 0001

    and that the data inputs need to be

    D = {D(A),D(B),D(C),D(D)} = 0001

    You might want to pay a bit closer attention to your table.

    Me, too.

    Of course you have to have some source of input come in. How is this counter supposed to know when you want it to reset and when you want it to count? It's not a mind reader!

    So let's just presume, for the moment, that you have in input signal called R and, when R is HI, you want the counter to go to the sate S={1000}, namely A to go HI and all the others to go LO.

    When R is LO, what do you want A to go to? Put it in terms of the outputs, A, B, C, and D.
     
  5. mikez

    Thread Starter Member

    Jan 21, 2013
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    The states that I am wanting to look at are: 0001, 0010, 0100, and 1000. I am not sure how I would map that out on my truth table.

    So lets see if I can be clear about what I am thinking of at the moment:

    I will have a relay of Flip-Flops: Labeled A-D (A being the first in the line and have the output of Q(0) and D being the last having the ouput of Q(3)). From my reading of ring counters the first FF will need to have a "1" passed to it to begin the chain. My instructions when assembling this small counter is that the ONLY input that I have will be the CLOCK. I do have a "Global" reset button on the MC that I can reset all of the FF's to 0's with the press of it. Would I want to look at the state that the button is in and have it send a signal to that to initially pass the "1" to my FF labeled A?

    Here is my problem though. I have an OR gate connected to D(0) (input to Flip-Flop(A) first in series) one input being that of the button and the other being Q(3).

    First pass:
    Button: 1
    Q(3): X (garbage - could be 0 or 1 -- unless I hit the reset button to make sure that I know there is a 0 in the last FF)

    Value going to FF(A) = 1

    FF(A) = 1
    FF(B) = 0
    FF(C) = 0
    FF(D) = 0

    Second pass:

    FF(A) = 0
    FF(B) = 1
    FF(C) = 0
    FF(D) = 0

    Third pass:

    FF(A) = 0
    FF(B) = 0
    FF(C) = 1
    FF(D) = 0

    Fourth pass:

    FF(A) = 0
    FF(B) = 0
    FF(C) = 0
    FF(D) = 1

    Fifth pass:

    Now that the output of Q(3) = 1 and that gets OR'd with my button which is inverted which would push "1" into FF(A).

    EDIT: I have no idea if that made sense at all. It seemed like a lot of incoherently babbling on my part - also I think with typing that I have given myself the idea of what I need to do to be able to solve my problem. Maybe someone can look over what I put up and see if it makes sense at all?
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    The phrase "relay of Flip-Flops" is pretty strange. A "relay" has a pretty specific meaning (actually, a couple of them) in EE and this ain't one of them. You might try, "set of flip-flops" or "bank of flip-flops". Minor point -- I know what you are trying to say.

    That's fine -- and it's why I explicitly said, "let's presume, for the moment...."

    The idea is to see how we might accomplish the goal IF we had an external signal and, once we understand what we need to do and how we can accomplish it with an external signal, THEN let's see if we can figure out how to generate that signal internally. It's all part of breaking the problem down into smaller pieces and solving the smaller, simpler problems one at a time.

    You could, but it might be easier said than done; if it is reseting all of your registers it might interfere with the very process of looking at its state unless you are very careful.

    But we don't have to know its state if we can settle for knowing, and detecting, its effect. Assuming we get this circuit working, we know that, when running, exactly one of the flip flops will be a 1 and the rest will be 0. The only time this isn't the case is following a global reset and, in that case, all of the flip flops will be 0. Can you think of a way to produce a signal (let's call it R), that is HI when the flip flops have just been reset and LO at all other times?

    Is this the reset button, or some other button?
    Yes, some of it was incoherent, but the gist came across pretty well.

    It is very often the case that if you really take the time to clearly communicate your problem to someone else, the very act of trying to do so forces you to think more clearly and precisely about the problem and the solution comes to you. When I'm designing a circuit or writing a computer program I often speak to an imaginary friend as though I am trying to explain the problem to them in great detail -- and I sometimes literally do this out loud to an empty chair and draw diagrams on the board and everything if I'm really struggling with something. It's amazing how often it works, too.

    From your babblings I was getting the impression that you were getting pretty close to the key point that you needed to see.
     
  7. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Have you considered a 2 stage Johnson counter with decoding?

    EDIT: Hmmm, if this is homework, it probably violates the problem definition.
     
    Last edited: Feb 1, 2013
  8. WBahn

    Moderator

    Mar 31, 2012
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    Gee, Ron, does he get to keep the silver platter?

    What ever happened to the notion of leading students toward the discovery of the a solution for themselves and not just handing them their problem completely worked for them?

    He was getting very close to coming up with a perfectly acceptable solution through his own struggles.

    Apparently this really is now the "Homework Done For You" forum.
     
  9. mikez

    Thread Starter Member

    Jan 21, 2013
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    Haha don't beat him up too much Wbahn. If I were able to use a Johnson Ring counter I probably would not be asking for advice or assistance. Oh I also was able to solve my problem. Apparently within the FPGA software I am able to select the initial state of my first FF to be 1 and the others being 0. However if I weren't able to do this I thought about it and what I would do is invert my GLOBAL reset signal and OR that with my output from my last FF. I would then have a second inverter after my first FF and I believe that would solve my problems. Hopefully I did that right...the napkin I scribbled this on while eating dinner was a bit hard to read after being up for almost 24 hours.
     
  10. WBahn

    Moderator

    Mar 31, 2012
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    I really, really wouldn't mess around with trying to use the Global Reset signal as both a reset and as part of the logic. You are just asking for race conditions to occur. Think about it -- your signal making the D input to the first FF only lasts as long as the GR is being asserted, but as long as the GR is being asserted, the first FF can't respond to any signalon the D input because it is being held in reset!

    Think about what I said earlier. What is the state of the counter after a global reset? It's all zeros, right? And it will stay all zeros until you get that first 1 injected into it. Well, can you think of a way to produce a 1 when, and only when, the output of the counter is all zeros? What would happen if you ORed that signal with the output of the final FF stage as it goes back to the D-input of the first stage?
     
  11. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Oops! I can't believe I violated my own rules about homework. I'm not sure what got into me.:(
     
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