4 bit comparator vhdl problem

Discussion in 'Programmer's Corner' started by limbonic, Oct 18, 2012.

  1. limbonic

    Thread Starter New Member

    Jul 4, 2011
    17
    0
    Hello,
    i want to make a structual description of a 4bit comparator using GENERATE stratements.

    my code is this:

    Code ( (Unknown Language)):
    1.  
    2. LIBRARY ieee;
    3. USE ieee.std_logic_1164.all;
    4. USE ieee.std_logic_arith.all;
    5.  
    6. ENTITY temp1 IS
    7.         port(Ain,Bin : in std_logic_vector(4 downto 0);        
    8.       PrevA,PrevB: in std_logic;
    9.       AgB, AlB: out std_logic);
    10. END ENTITY temp1;
    11.  
    12. --
    13. ARCHITECTURE structural OF temp1 IS
    14.         signal s1,s2,s3,s4,s5,s6: std_logic;
    15. component bit_slice_comp is
    16.      port(A,B : in std_logic;        
    17.       PrA,PrB: in std_logic;
    18.       AgBout, AlBout: out std_logic);
    19.     end component bit_slice_comp;
    20.  
    21. Begin
    22.   comp_iterate: for i in 0 to 3 generate
    23.   comp: bit_slice_comp port map (A=> Ain(i), B=> Bin(i), PrA => PrevA, PrB => PrevB, AgBout => AgB, AlBout =>AlB);
    24.  --  comp: bit_slice_comp port map ( Ain(i)=>A,  Bin(i)=>B,  PrevA => PrA,  PrevB => PrB,  AgB => AgBout , AlB => AlBout );
    25.  
    26.       calculation: process
    27.       begin
    28.       s1<= Ain(i) and PrevA;
    29.       s2<= Ain(i) and (not Bin(i));
    30.       s3<= (not Bin(i)) and PrevA(i);
    31.        
    32.       s4<= PrevB(i) and Bin(i);
    33.       s5<= Ain(i) and PrevB(i);
    34.       s6<= (not Ain(i)) and Bin(i);  
    35.        
    36.       AgB <= s1 or s2 or s3;
    37.       AlB <= s4 or s5 or s6;
    38.     end process calculation;
    39.   end generate;
    40. END ARCHITECTURE structural;
    41.  
    42.  
    When i try to compile i have this mistakes:

    Code ( (Unknown Language)):
    1.  
    2. * Error: temp1_structural.vhd(38): Prefix of indexed name must be an array.
    3. ** Error: /temp1_structural.vhd(38): Type error resolving infix expression "and" as type ieee.std_logic_1164.std_logic.
    4. ** Error:temp1_structural.vhd(40): Prefix of indexed name must be an array.
    5. ** Error:temp1_structural.vhd(40): Type error resolving infix expression "and" as type ieee.std_logic_1164.std_logic.
    6. ** Error: temp1_structural.vhd(41): Prefix of indexed name must be an array.
    7.  ** Error: temp1_structural.vhd(41): Type error resolving infix expression "and" as type ieee.std_logic_1164.std_logic.
    8. ** Warning: [2] temp1_structural.vhd(46): (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
    9. ** Error: temp1_structural.vhd(48): VHDL Compiler exiting
    Anyone could Help? Thanks!
     
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