4-bit adder using 2 2-bit adder VHDL

Discussion in 'Homework Help' started by qw111, Sep 23, 2010.

  1. qw111

    Thread Starter New Member

    Sep 23, 2010
    1
    0
    Im trying to implement a 4-bit adder using 2 2-bit adders instead of 4 full adders using port maps in VHDL.
    I have already done it with 4 full adders but I am having trouble with 2 2-bit adders.
    Code ( (Unknown Language)):
    1. Library ieee;
    2. Use ieee.std_logic_1164.all;
    3.  
    4. Entity Four_Bit_Adder is
    5. Port
    6. (
    7. I0,I1 : in STD_LOGIC_VECTOR(3 downto 0);
    8. Cin : in STD_LOGIC;
    9. S   : out STD_LOGIC_VECTOR(3 downto 0);
    10. Cout    : out STD_LOGIC
    11. );
    12. End Four_Bit_Adder;
    13.  
    14. Architecture arch of Four_Bit_Adder is
    15.  
    16. Component Full_Adder
    17. Port
    18. (
    19. A,B,Cin : in std_logic;
    20. S,Cout  : out std_logic
    21. );
    22. End component;
    23.  
    24. Signal Temp : STD_LOGIC_VECTOR(2 downto 0);
    25.  
    26. begin
    27.  
    28. FA1: Full_Adder port map
    29. (
    30. A => I0(0),
    31. B => I1(0),
    32. Cin => Cin,
    33. S => S(0),
    34. Cout => Temp(0)
    35. );
    36.  
    37. FA2: Full_Adder port map
    38. (
    39. A => I0(1),
    40. B => I1(1),
    41. Cin => Temp(0),
    42. S => S(1),
    43. Cout => Temp(1)
    44. );
    45.  
    46. FA3: Full_Adder port map
    47. (
    48. A => I0(2),
    49. B => I1(2),
    50. Cin => Temp(1),
    51. S => S(2),
    52. Cout => Temp(2)
    53. );
    54.  
    55. FA4: Full_Adder port map
    56. (
    57. A => I0(3),
    58. B => I1(3),
    59. Cin => Temp(2),
    60. S => S(3),
    61. Cout => Cout
    62. );
    63.  
    64. End arch;
    65.  
    How do you go about using port maps for the 2 2-bit adders?
    I also have created a 2-bit adder code:
    Code ( (Unknown Language)):
    1.  
    2.  
    3. Library ieee;
    4. Use ieee.std_logic_1164.all;
    5.  
    6. Entity Two_Bit_Adder is
    7. Port
    8. (
    9. A0, A1, B0, B1      : in STD_LOGIC;
    10. Cin         : in STD_LOGIC;
    11. S0, S1          : out STD_LOGIC;
    12. Cout            : out STD_LOGIC
    13. );
    14. End Two_Bit_Adder;
    15.  
    16. Architecture arch of Two_Bit_Adder is
    17.  
    18. Component Full_Adder
    19. Port
    20. (
    21. A, B, Cin   : in std_logic;
    22. S, Cout     : out std_logic
    23. );
    24. End component;
    25.  
    26. Signal Temp : std_logic;
    27.  
    28. begin
    29.  
    30. FA1: Full_Adder port map
    31. (
    32. A => A0,
    33. B => B0,
    34. Cin => Cin,
    35. S => S0,
    36. Cout => Cout
    37. );
    38.  
    39. FA2: Full_Adder port map
    40. (
    41. A => A1,
    42. B => B1,
    43. Cin => Temp,
    44. S => S1,
    45. Cout => Cout
    46. );
    47.  
    48. End arch;
    49.  
    I'm assuming I need to have two_bit_adder as a component but as far as the port map goes, I am stuck.
     
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