4-bit adder using 2 2-bit adder VHDL

Thread Starter

qw111

Joined Sep 23, 2010
1
Im trying to implement a 4-bit adder using 2 2-bit adders instead of 4 full adders using port maps in VHDL.
I have already done it with 4 full adders but I am having trouble with 2 2-bit adders.
Rich (BB code):
Library ieee;
Use ieee.std_logic_1164.all;

Entity Four_Bit_Adder is
Port
(
I0,I1 : in STD_LOGIC_VECTOR(3 downto 0);
Cin	: in STD_LOGIC;
S	: out STD_LOGIC_VECTOR(3 downto 0);
Cout	: out STD_LOGIC
);
End Four_Bit_Adder;

Architecture arch of Four_Bit_Adder is

Component Full_Adder
Port
(
A,B,Cin	: in std_logic;
S,Cout	: out std_logic
);
End component;

Signal Temp : STD_LOGIC_VECTOR(2 downto 0);

begin

FA1: Full_Adder port map
(
A => I0(0),
B => I1(0),
Cin => Cin,
S => S(0),
Cout => Temp(0)
);

FA2: Full_Adder port map
(
A => I0(1),
B => I1(1),
Cin => Temp(0),
S => S(1),
Cout => Temp(1)
);

FA3: Full_Adder port map
(
A => I0(2),
B => I1(2),
Cin => Temp(1),
S => S(2),
Cout => Temp(2)
);

FA4: Full_Adder port map
(
A => I0(3),
B => I1(3),
Cin => Temp(2),
S => S(3),
Cout => Cout
);

End arch;
How do you go about using port maps for the 2 2-bit adders?
I also have created a 2-bit adder code:
Rich (BB code):
Library ieee;
Use ieee.std_logic_1164.all;

Entity Two_Bit_Adder is
Port
(
A0, A1, B0, B1		: in STD_LOGIC;
Cin			: in STD_LOGIC;
S0, S1			: out STD_LOGIC;
Cout			: out STD_LOGIC
);
End Two_Bit_Adder;

Architecture arch of Two_Bit_Adder is

Component Full_Adder
Port
(
A, B, Cin	: in std_logic;
S, Cout		: out std_logic
);
End component;

Signal Temp : std_logic;

begin

FA1: Full_Adder port map
(
A => A0,
B => B0,
Cin => Cin,
S => S0,
Cout => Cout
);

FA2: Full_Adder port map
(
A => A1,
B => B1,
Cin => Temp,
S => S1,
Cout => Cout
);

End arch;
I'm assuming I need to have two_bit_adder as a component but as far as the port map goes, I am stuck.
 
Top