Hi everyone,

I have a 4 bit add/sub circuit I must design and I have the design all laid out. However, testing it in LabView with my professors program, there is a glitch that gives a negative zero for the output. My thinking is I need an XOR gate somewhere on the sign wire but am unsure. Any help will be much appreciated!

 

You designed it...
But we supposed to troubleshoot it...

Anybody else has a problem with that?

 

You designed it...
But we supposed to troubleshoot it...

Anybody else has a problem with that?

I have tried running through the circuit but can't find where the problem is occuring. What is the problem with asking for a little help?

 

What input did you give A and B and what was the output?

 

Let's start with the representation of numbers. Is it

1. 2's complement
2. 1's complement
3. Something Else

The reason I ask is that negative zero is a very odd concept in normal binary arithmetic, except in 1's complement notation.
Focusing on a sign bit is odd since it is part of the normal operation in both 1's and 2's complement notation. You really need to do a better job of explaining what you're trying to do and what you think is wrong because for the life of me I can't figure out what you're talking about.

 

As others have stated/implied, the problem isn't with asking for help or guidance. The problem is that you present us a schematic that is supposed to be your solution and then ask us to tell you what is wrong with it (even if only asking for a hint). Why that is a problem is that to troubleshoot your design, you are forcing us to reverse engineer your entire design and then do some guessing as to why you did what you did and what you might have intended it to do. The better thing would be to describe how your design is supposed to accomplish its task, so that we can focus on determining whether your approach is wrong or whether your implementation doesn't match your approach.

At first glance, a question I have is why your sign signal is dependent on whether you are doing an add or a subtract. Isn't the result either positive or negative, regardless of what operation was performed in order to get that result?

 

And the last thing you want to do at this point is cop an attitude because we're having difficulty giving you precisely what you want or expect. Take a deep breath, step back, and ask yourself if there is anything you can do or say that will help us understand what is going on?

 

And the last thing you want to do at this point is cop an attitude because we're having difficulty giving you precisely what you want or expect. Take a deep breath, step back, and ask yourself if there is anything you can do or say that will help us understand what is going on?

Sorry if it came off as having a bad attitude, wasn't my intentions. I would also like to apologize to sheteii01 and everyone for approaching with my question the wrong way. I see how it came across as just asking someone to troubleshoot it for me, my apologies.


To give more information for my problem, it only occurs when I put the input for A and B to 15 and subtract it. Here is how it flows through with red circles = 1 and green=0 . and the output giving a negative 0.

 

My question still stands. Why do you have your sign signal logic depending on whether you are adding or subtracting? Furthermore, what is the purpose of the four XOR gates at the bottom?

As someone else asked earlier, what is the representation of your four-bit values? 2's comp? 1's comp? Signed binary? Something else?

I can't quite tell what the far left signals are to your adder -- is the top one a Carry In and the bottom on a Carry Out? If so, why does the Carry Out feed back into the Carry In?

 

At this moment I can't answer your first question trying to figure why it it that way. The four XOR gates are the outputs for the answer, in this case it would be zero. For the circuit I believe its represented in 1's comp. The top is a carry in and the bottom is a carry out. I believe it is feed back if there is a 1 carry to add back into the number.

 

It is true that using a 1's complement representations has bot +0 and -0. To get the correct result requires an end around carry be added to the result once the value of the carry out is known.

 

Hello DevTom.

In your design, top to bottom:
The first XOR gates are used in your circuit to take the two's complement.
When in the subtraction function is when used.

The next XOR gates are to get a result when you subtract a larger number of other minor. (10 - 15).

In your design you have something that you must discover, wrong connected.
Analyze the circuit contained in the PDF document attached to you.

The attached ZIP file contains the Proteus ISIS simulation.

:

 

At this moment I can't answer your first question trying to figure why it it that way. The four XOR gates are the outputs for the answer, in this case it would be zero. For the circuit I believe its represented in 1's comp. The top is a carry in and the bottom is a carry out. I believe it is feed back if there is a 1 carry to add back into the number.

So I'm a bit confused -- where did this circuit come from? I was under the impression that this was a circuit you designed to try to implement signed addition/subtraction.

 

Hello DevTom.

In your design, top to bottom:
The first XOR gates are used in your circuit to take the two's complement.
When in the subtraction function is when used.

The next XOR gates are to get a result when you subtract a larger number of other minor. (10 - 15).

In your design you have something that you must discover, wrong connected.
Analyze the circuit contained in the PDF document attached to you.

The attached ZIP file contains the Proteus ISIS simulation.

:

Wow thanks for this. I was running through the simulation and I believe I fixed my issue. Thanks again.

 

Actually, the XOR gates at the top takes the 1's complement. This, combined with the artificial Carry In from the Subtract flag being HI is what produces the 2's complement.