3 Cycle overhead too much?

Discussion in 'Embedded Systems and Microcontrollers' started by jcia, Jan 26, 2010.

  1. jcia

    Thread Starter New Member

    Dec 9, 2008
    4
    0
    Hi All,

    I have another problem and hopefully you can help me, so I am doing a BSL for a MSP430 chip and I needed to change the Interrupt vector and create a new Intermediary one, which basically does a Branch to the Main application (outside BSL area) ISR. By doing this, I am basically adding a 3 cycle overhead, right? being a branch instruction a flush of the pipeline has to be done creating this 3 cycle overhead in calling the actual interrupt handler. But in testing I can see a lot of lag in comparison with the jump directly from the Interrupt vector (no intermediary), my microcontroller's CPU is running on a 12Mhz clock so 3 cycles shouldn't give a lot of delay. Like I can visually see that is taking a lot longer, 3 cycles amount to ~250ns which normally one shouldn't notice that much right?

    What other problem do you think might be happening that makes the delay a lot longer than what I am expecting?
     
    Last edited: Jan 26, 2010
  2. jcia

    Thread Starter New Member

    Dec 9, 2008
    4
    0
    Hi,

    I solved the problem, it was my error (as almost always), I was doing many changes to the ISR's that at one point I deleted I deleted the instruction at the end of the ISR to wake up from Low Power Mode, so basically when the delay timer went into the interrupt it handled the interrupt but didn't wake the process that was waiting for it, so the process woke on another interrupt at a later point thus creating a visible lag. Now it's working.
     
  3. atferrari

    AAC Fanatic!

    Jan 6, 2004
    2,644
    759
    Let's say that you got somehow a good balance, because there, you repeated you repeated. :D
     
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