Hi All,
I have another problem and hopefully you can help me, so I am doing a BSL for a MSP430 chip and I needed to change the Interrupt vector and create a new Intermediary one, which basically does a Branch to the Main application (outside BSL area) ISR. By doing this, I am basically adding a 3 cycle overhead, right? being a branch instruction a flush of the pipeline has to be done creating this 3 cycle overhead in calling the actual interrupt handler. But in testing I can see a lot of lag in comparison with the jump directly from the Interrupt vector (no intermediary), my microcontroller's CPU is running on a 12Mhz clock so 3 cycles shouldn't give a lot of delay. Like I can visually see that is taking a lot longer, 3 cycles amount to ~250ns which normally one shouldn't notice that much right?
What other problem do you think might be happening that makes the delay a lot longer than what I am expecting?
I have another problem and hopefully you can help me, so I am doing a BSL for a MSP430 chip and I needed to change the Interrupt vector and create a new Intermediary one, which basically does a Branch to the Main application (outside BSL area) ISR. By doing this, I am basically adding a 3 cycle overhead, right? being a branch instruction a flush of the pipeline has to be done creating this 3 cycle overhead in calling the actual interrupt handler. But in testing I can see a lot of lag in comparison with the jump directly from the Interrupt vector (no intermediary), my microcontroller's CPU is running on a 12Mhz clock so 3 cycles shouldn't give a lot of delay. Like I can visually see that is taking a lot longer, 3 cycles amount to ~250ns which normally one shouldn't notice that much right?
What other problem do you think might be happening that makes the delay a lot longer than what I am expecting?
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