3 bit up counter verilog code

Discussion in 'Programmer's Corner' started by vead, Jan 18, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
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    someone help me to write verilog code for 3 bit up counter
    N A B C next state
    0 0 0 0 001
    1 0 0 0 001
    2 0 1 0 011
    3 0 1 1 100
    4 1 0 0 101
    5 1 0 1 110
    6 1 1 0 111
    7 1 1 1 000


    module up_counter (A,B,C,clk A' B' C')
    input clk
    output
    reg 3:0
     
    Last edited: Jan 18, 2014
  2. t06afre

    AAC Fanatic!

    May 11, 2009
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    Vead this site has a lot of working examples. I suggest you take a look at it. http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode.html
    If you still are stuck you are more than welcome to ask for help here. But at least try using google/youtube before asking for help in this forum. That is the purpose of this forum. It is a help to helping oneself. Not a private personal teacher
    It is a lot good material on web regarding VHDL coding. Then it comes to programming you can learn a lot by looking at working code examples and understanding them. After that try to do some experiments with code.
     
  3. vead

    Thread Starter Active Member

    Nov 24, 2011
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    thanks for reply I don't want to complete someone whole code. before posting on forum I googled for up counter verilog code and I saw lot of example because of my previous knowledge I know the basic table I have read ,before going to design hardware in verilog we need to know the function table I confused here how to write assignment statement for this counter
     
  4. tshuck

    Well-Known Member

    Oct 18, 2012
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    First, let's figure out the answer to my question in your other thread: is there a specific modelling technique you are required to use? From your recent string of threads, I would assume you are required to use structural, but confirmation would allow us to move along.
     
  5. WBahn

    Moderator

    Mar 31, 2012
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    Then perhaps a better place for you to start is to understand assignment statements in general.

    Regardless, we need to see YOUR best attempt at a solution.
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    That's a rather strange up counter, don't you think. What happens if it is in state 001?
     
  7. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    sorry that was wrong table It was my mistake
    table for counter

    N | A B C(current state) clk |next state
    0 | 0 0 0 | ↑ 001
    1 | 0 0 1 | ↑ 010
    2 | 0 1 0 | ↑ 011
    3 | 0 1 1 | ↑ 100
    4 | 1 0 0 | ↑ 101
    5 | 1 0 1 | ↑ 110
    6 | 1 1 0 | ↑ 111
    7 | 1 1 1 | ↑ 000
    I try to write code but not sure that code is correct
    Code ( (Unknown Language)):
    1. module up_counter(current state, next state ,clk)
    2.           input current state ;
    3.           input clk;
    4.           output next state;
    5.           reg 3:0
    6.           always @ (posedge clk);
    7.           begin
    8.           next state <= current state +1 ;
    9.           end
    10.          endmodule
     
    Last edited: Jan 19, 2014
  8. WBahn

    Moderator

    Mar 31, 2012
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    Think about this code. Is that how a counter chip works? Do you have a bunch of input pins on which you have to provide a "current state" value and then on the rising clock edge the counter chip outputs what is on the input incremented by 1? And what does it put out on the output pins before the clock goes HI?

    Remember, your HDL code has to describe the complete behavior of a piece of hardware. Don't make or expect the tool to guess what you want.
     
  9. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
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    there is bunch of input and output so i confused how to declare the input and output port can you tell me how to declare
     
  10. Brownout

    Well-Known Member

    Jan 10, 2012
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    998
    That's pretty how it works. I will only say we typically don't use "state" as a variable when coding counters. We usually reserve those vairable names for actual state machines. You can make the counter a state machine, but what you have here is the way it's almost always done, and the way it should be done. Also, you want to just increment the value, you don't need the extra vairable you have defined as "next." So, use "inout" for the port direction for the variable.

    As you progress in digital design, you'll make state machines, where the state/next state idea from your charts will be used directly in your code.

    You have a couple syntax errors, you'll find them when you attempt to compile your code.
     
    Last edited: Jan 19, 2014
  11. WBahn

    Moderator

    Mar 31, 2012
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    I'm pretty sure he has just three signals, current_state, next_state, and clk.

    I don't follow your assertion that this is how a counter should be done. When you use a counter, don't you expect the counter to keep track of what the count is? And shouldn't the value of the output be defined for the time before the clock's rising edge?
     
  12. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Not sure what you're refering to. Here's what I'm talking about.


    Code ( (Unknown Language)):
    1.  
    2. module counter( input clk, inout reg [2:0] count)
    3.  
    4. ...
    5.  
    6. count <= count + 1;
    7.  
    8. ...
    9.  
    10. endmodule
    11.  
     
  13. vead

    Thread Starter Active Member

    Nov 24, 2011
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    If we know the function table of any logic circuit then we can write code in verilog but here is I am totally confused I don't know how to declare port and how to make loop
     
  14. WBahn

    Moderator

    Mar 31, 2012
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    Why do you need a loop? You functional description says, "Upon seeing a rising edge on the clock, if in this state go to that state." No loop.
     
  15. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
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    I mean assignment statement
     
  16. WBahn

    Moderator

    Mar 31, 2012
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    There's a HUGE difference between "loop" and "assignment statement"! :eek:

    Please take more care in proofing your posts so that we don't waste a bunch of time chasing you down rabbit holes.
     
  17. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    hello again my aim is to find out input and output for counter so that I can write the verilog code Now I made the present state and next state table than What i do next i think I need to drive the K map for present state help me please
     
  18. tshuck

    Well-Known Member

    Oct 18, 2012
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    Vead,
    Please take some time and look at a generic counter circuit.
    [​IMG]
    How many inputs to the counter do you see? And how many outputs?

    The flip flops are a part of the counter, they aren't inputs and their inputs are not necessarily the inputs to the counter.
     
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