So I have to analyze a 3 bit synchronous counter much like this:
From that I'm supposed to supply:
1. A state table
2. A state diagram
3. A timing diagram.
I know what a state table, state diagram, and timing diagram are so that base is covered, but what my question is... what the <snip>?
I read the chapter in my book and it was no help. I went to the internet and found this video:
http://www.youtube.com/watch?v=aommEKcT3go&feature=relmfu
But it really only covers 2 bit, not 3 bit. When he does do 3 bit he does something covering only even numbers.. I don't know. It helped a little bit, but not so much. Especially since he did the process backwards to create a synchronous counter, rather than what I need which is finding the specifications behind the diagram.
What I do understand:
The AND gates make it so the inputs must be logic HIGH in order to press on. Other than that, this whole thing has me stumped.
I would appreciate any help. Whether it be someone explaining it or just linking me to some material. I'll actually read it too
From that I'm supposed to supply:
1. A state table
2. A state diagram
3. A timing diagram.
I know what a state table, state diagram, and timing diagram are so that base is covered, but what my question is... what the <snip>?
I read the chapter in my book and it was no help. I went to the internet and found this video:
http://www.youtube.com/watch?v=aommEKcT3go&feature=relmfu
But it really only covers 2 bit, not 3 bit. When he does do 3 bit he does something covering only even numbers.. I don't know. It helped a little bit, but not so much. Especially since he did the process backwards to create a synchronous counter, rather than what I need which is finding the specifications behind the diagram.
What I do understand:
The AND gates make it so the inputs must be logic HIGH in order to press on. Other than that, this whole thing has me stumped.
I would appreciate any help. Whether it be someone explaining it or just linking me to some material. I'll actually read it too
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