3 bit synchronous counter

Discussion in 'Homework Help' started by Prototape, Apr 11, 2011.

  1. Prototape

    Prototape Thread Starter New Member

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    So I have to analyze a 3 bit synchronous counter much like this:

    [​IMG]

    From that I'm supposed to supply:

    1. A state table
    2. A state diagram
    3. A timing diagram.

    I know what a state table, state diagram, and timing diagram are so that base is covered, but what my question is... what the <snip>?

    I read the chapter in my book and it was no help. I went to the internet and found this video:

    http://www.youtube.com/watch?v=aommEKcT3go&feature=relmfu

    But it really only covers 2 bit, not 3 bit. When he does do 3 bit he does something covering only even numbers.. I don't know. It helped a little bit, but not so much. Especially since he did the process backwards to create a synchronous counter, rather than what I need which is finding the specifications behind the diagram.

    What I do understand:
    The AND gates make it so the inputs must be logic HIGH in order to press on. Other than that, this whole thing has me stumped.

    I would appreciate any help. Whether it be someone explaining it or just linking me to some material. I'll actually read it too :p
    Last edited by a moderator: Apr 11, 2011
  2. Georacer

    Georacer Moderator Staff Member

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    First, check here: http://www.allaboutcircuits.com/vol_4/chpt_11/3.html
    It might not add much, but anything helps.

    Can you post any of your efforts to solve the problem? Try to complete the state diagram at least. We require you to do a bit of effort before receiving help here.

    But 3 bits aren't that different from 2bits really...
  3. Prototape

    Prototape Thread Starter New Member

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    I checked that out but it didn't help much :/
    I wasn't necessarily asking people to finish my homework for me, I just need something to start me off, I come here as a last resort because there's more people who need help.

    My attempt at a state diagram consisted of J and K 0-2 to be all logic HIGHs. From what I can tell, the diagram says that J0 and K0 are 1 as per the 1 behind them. From there, I suspected J1 and K1 must be high, referring to the AND gate which states that all inputs must be high to give output high. J2 and K2 must also be high in order to keep the sequence going, but K would have to be a 0 to repeat, correct?

    I have no idea if that's right, but it's just the hunch I got. This whole thing pretty much confused me, though.
  4. Georacer

    Georacer Moderator Staff Member

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    Ok, you can start by the state diagram. At first assume that all 3 FFs have 0 internal state. That means that you are at the 000 state count. Check what the output will be.

    Now notice that the J and K inputs are either constant (J0, K0) or a function of the current outputs. That lets you build the inputs for the next cycle, and eventually build the whole diagram.

    For example, after starting from 000, you have:
    J0=1, K0=1
    J1=(1 AND 0)=0, K1=0
    J2=(0 AND 0)=0, K2=0
    Therefore the next state will be 100.

    Continue this way to construct the whole state diagram (which of course you know it's a simple 3-bit count).

    Once you have your diagram, the rest is easy. Check here http://www.allaboutcircuits.com/vol_4/chpt_11/5.html for a tutorial.
    I think what you ask is the first table of the tutorial.

    Is that clear?
  5. Prototape

    Prototape Thread Starter New Member

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    Aaaah. That cleared things up quite a bit, thank you!
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