Hi,

I've been stuck on this question for 2 hours now and i can't figure out the best way to approach the problems.

The problems is that i need to draw a schematic of a 3-bit synchronous counter using D Flip flops that counts in the following sequence. 111->010->011->001->101->110->000->111

help much appreciated.

 

I'm too busy to do it myself now but THIS document gives you step by step instructions on how to implement it with D-FFs.

Have fun

 

You want to think about each output bit individually. Think about how each bit is affected by the present outputs of your flip flops.

 

I'm too busy to do it myself now but THIS document gives you step by step instructions on how to implement it with D-FFs.

Have fun

Thanks very much for the document!! I followed everything and from the Karnaugh Maps i got:-
Da = |B
Db = |C|A + CA
Dc = |A

I'm not too sure how to represent Db in a circuit, is it a 4 input OR gate?

Please check out the diagram i made below, logisim gives me these output 111->010->011->011->011....

 

I'm not too sure how to represent Db in a circuit, is it a 4 input OR gate?

Your Karnaugh maps are good. |A|C + AC is actually two ANDs connected to an OR gate, where the inputs of one of the AND are inverted. Almost there....

It's "|Qa AND |Qc" OR "Qa AND QC".

 

Your Karnaugh maps are good. |A|C + AC is actually two ANDs connected to an OR gate, where the inputs of one of the AND are inverted. Almost there....

It's "|Qa AND |Qc" OR "Qa AND QC".

Thanks so much for your help, now i have a better understand. Karnaugh maps seem to be pretty useful I've never heard of them before.

Thanks again!

 

Now, to make it even MORE interesting:

|A|C + AC is actually two ANDs connected to an OR gate, where the inputs of one of the AND are inverted. Almost there....

That solution requires two AND gates, one OR gate, and two inverters. Five logic functions to get that output; and those functions would be in three separate IC's.

However, if you select a more obscure gate, you could accomplish that function with only TWO of that same gate - and both gates are in one IC, and you'd have more to spare.

Which gate am I thinking about?

 

Now, to make it even MORE interesting:


That solution requires two AND gates, one OR gate, and two inverters. Five logic functions to get that output; and those functions would be in three separate IC's.

However, if you select a more obscure gate, you could accomplish that function with only TWO of that same gate - and both gates are in one IC, and you'd have more to spare.

Which gate am I thinking about?

Two gates only?? I could only simplify it by using three NAND gates.

My final diagram looked like

 

Now, to make it even MORE interesting:


That solution requires two AND gates, one OR gate, and two inverters. Five logic functions to get that output; and those functions would be in three separate IC's.

However, if you select a more obscure gate, you could accomplish that function with only TWO of that same gate - and both gates are in one IC, and you'd have more to spare.

Which gate am I thinking about?

I knew that someone would propose a better solution. I was too lazy to do it...

If you put the expression A'C' + AC in a normal truth table it will get instantly clear what gate Wookie meant. If you use D-FFs with inverted outputs you also need only one gate.

The inputs of your function are either BOTH "0" OR they are BOTH "1".

 

Well, if you keep thinking about it, you'll realize that an eXclusive OR gate is sort of like an OR gate, where if any input is 1, then the output is also 1 - except the XOR gate will output a 0 if BOTH inputs are 1.

So, with an XOR gate, it outputs a 0 if both inputs are equal, and a 1 if the inputs are not equal - which is just the opposite of what you need.

So, what happens if you put an inverter on one of the inputs? Did you know that you can use an XOR gate as a selectable inverter/non-inverter? If you hold one input low, whatever goes in the other input is passed to the output; if you hold one input high, the other input appears on the output inverted. So, if you use an XOR gate as an inverter on either input - OR the output - you will wind up with the function you need - so that's two of the same gate, leaving two more two-input XOR gates in the IC package.

But, you can go one step further, and use an XNOR gate, which is basically an XOR gate with an inverter on the output. Instead of requiring that the inputs are unequal for a 1 output, else 0 out, now the output is 1 only if both inputs are equal (both 1's or both 0's) - which is what you need.

Wikipedia has a summary of the basic logic gates and their truth tables:
http://en.wikipedia.org/wiki/Logic_gate

 

In the pdf document linked in the 2nd post it says in part 4 on page 4
that Da = |B + |C
I'm getting B XOR C instead.
Can someone check this to see if it's wrong.

 

In the pdf document linked in the 2nd post it says in part 4 on page 4
that Da = |B + |C
I'm getting B XOR C instead.
Can someone check this to see if it's wrong.

AB = 00 is an undefined condition. (not allowed) DA would have to be "1" to have B XOR C.

 

Since B remains constant shouldn't it be included?

 

B is included, it is a part of a group of 4 top give you a B'...

 

This case is covered by C = "0". And you have to use "C" to make sure that if "C" is "1" then "DA" is "0".

Or am I not getting your question?

 

For the Da column, doesn't each first digit represent A and the 2nd represent B?
So
00 means A = 0 B = 0
01 means A = 0 B = 1
11 means A = 1 B = 0
10 means A = x B = 1

So then for the two 1's in the C=0 column
we draw a circle around them since they're adjacent and
A changes between the two so it's not included in the term.
B remains as 1 so it's included.
C remains as 0 so it's included.

This gives us
B AND |C

For the 1 in the bottom right hand corner A B and C remain constant so they're all
included.
We get A.C.|B
So the end result is Da = B.|C + A.C.|B
which apparently is incorrect. Can someone tell me where im going wrong?

 

You're not wrong, you just chose not to utilize the unused state bits in your minimization (which is fine). In the PDF the unused states are treated as 'don't cares' (i.e. when grouping, each 'x' can be treated as a 1 or 0 to aid in minimization.)

Don't cares simplify the logic but can sometimes cause problems if a glitch ever causes the system to enter one of the unused states (since arbitrary state transisitons are being assigned to these unused states.)

 

ok thanks. that diagram cleared things up.

I'm having difficulty understanding how to create a k map from the given state tables. Could you explain that to me?

 

http://www.allaboutcircuits.com/vol_4/chpt_8/10.html talks about K-maps and how to utilize "do-not-care states" i.e. states that are not used by your circuit.

To get to the K-map, generate a truth table from the values that you want your counter to cycle through, those not included are the do-not-care states.

 

ok thanks. that diagram cleared things up.

I'm having difficulty understanding how to create a k map from the given state tables. Could you explain that to me?

If you are using D flip-flops you can simply fill the k-map for each flip-flop with the corresponding next-state values from the state table.

If you are using JK/SR/T flip-flops you need to use an excitation table to map each state transition to the appropriate flip-flop input level. The image attached below shows how this works:

The state transition I circled in the state table (bottom left) is from 6 (110) to 5 (101), this requires the C flip-flop to transition from a 0 to a 1 (red lines.)
To generate this transition using a JK flip-flop, the excitation table (top-left) shows a J input of '1' and a K input of 'x' (don't-care.) So, in the J and K k-maps for the C flip-flop, state 6 (110) will get a '1' and an 'x' respectively (blue lines.)

You repeat this process for each line of the state table and for each flip-flop (A, B and C). Note that when the state transition is to a don't-care, both J and K are set to 'x' - as in states 0, 1 and 4.)

In the end you'll have six k-maps (two for each flip-flop). Minimize these to get the input feedback logic for the JK flip-flop.