2 Level 16 bit Carry lookahead adder

Discussion in 'Homework Help' started by laguna92651, Apr 21, 2008.

  1. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
    101
    0
    I would be grateful if I could get some help by April 23.

    I think this is a fairly straight problem for someone who understands 2 level carry lookahead adders. I can send you the circuit diagrams for the adder.

    The question:
    I need to calculate the maximum propagation delay time for a 2 level 16 bit carry lookahead adder, assuming each gate introduces a unit time of propagation delay. The answer will need to show the path and components of the delay.



    Thanks
     
  2. Papabravo

    Expert

    Feb 24, 2006
    10,148
    1,791
    We are primarily hobbyists and experimenters. We would hardly ever have occasion to comtemplate something like that problem since it is chiefly in the relm of ASIC designers.

    If you have the schematic or the VHDL then it should be a simple matter of running the simulation to get an idea of the answer and going back to do the calculation.

    I never open MS Word documents from forums. The risks are just too great.
     
  3. Caveman

    Active Member

    Apr 15, 2008
    471
    0
    Put up the schematic of the single adder stages.
     
  4. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
    101
    0
    Attached is the circuit for a single level cla adder. (b) is single bit adder, is that what you want?
     
  5. Caveman

    Active Member

    Apr 15, 2008
    471
    0
    You just count it with a dash of logic to simplify.

    First note that for all of the single bit adders to output p and g is one delay from input changing.

    Also note that the S outputs from the single bit adders need one additional delay from the inputs than C, but C must come back from the lookahead generators in most cases, so the carry delay will define these paths.

    And the four lower lookahead generators will all have the same delay for their g outputs, and they will all have the same delay for their p outputs. However, the p delays may not equal the g delays.

    You have three basic path lengths:
    S16 since it is different from all others.
    S15-S4 requires a bit of attention to see, but these are all the same delay. This is because a lookahead generator with with simultaneous p inputs and simultaneous g inputs will output all carries with the same delay.

    S3-S0 are a little faster than the upper bits because C0 is available immediately. Since we are looking for maximum delay, we can ignore this.

    So, all you have to do is look at the delays of S16 and S15 to cover them all.
    I think S16 is 5 delays and S15 is 6. So 6 delays.
     
  6. abettino

    New Member

    Jan 12, 2012
    4
    0
    I came across this thread when searching for more information on carry look ahead adders. It looks like it might be a little out of date now but I found this link for how to design a carry look ahead adder in verilog This may be useful for others who find this thread!
     
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