# 2 bit comparator

Discussion in 'Homework Help' started by ol'trusty, Sep 10, 2010.

1. ### ol'trusty Thread Starter Member

Sep 9, 2009
48
0
How to make one using 2 1 bit comparators ?

Trusty

2. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
Do you know how a 1-bit comparator works? Do you have a specific one in mind? Summarize its principles, and the solution to your question will become more obvious.

3. ### ol'trusty Thread Starter Member

Sep 9, 2009
48
0
Well it has 2 inputs a and b
3 outputs y0 y1 y2 for a>b , a<b , a=b

What I actually need to do is to write a VHDL code making a 2 bit comparator out of two 1 bit comparators..

Thanks

4. ### Ghar Active Member

Mar 8, 2010
655
72
Do what you always do to design a simple logic function - make a truth table.

5. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
Well, I can't help you with the VHDL, but the logic to combine the 2 comparators is the following:

Set the first comparator to examine the most significant bit of each number. In case of inequality, you have your answer. In case of equality, let that signal be an "allow" signal for the second comparator, wich will examine the second bit of each number. The result of that comparator will be definite.

Does it make sense, or should I explain it a bit more?

6. ### ol'trusty Thread Starter Member

Sep 9, 2009
48
0
I think this does it.

Yes Geo that makes sense ! Thats where I was stuck , in the case of equality..

Last edited: Sep 11, 2010
7. ### ol'trusty Thread Starter Member

Sep 9, 2009
48
0
I might have done this the hard way .

What do you guys think ?

Thanks for all the help

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8. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
First off, it is a mistake to connect hardwired two logic signals, it just doesn't work. So, what you have done with the ">" and "<" outputs of the middle comparator is wrong.

Also, you don't need more than 2 comparators to do the job. Have the MSB comparator suppress the output of the other comparator when it's not giving "=" result. This can be done by filtering the outputs of the LSB comparator with 3 AND gates, 1 for each output. Each output will be connected to a 2-input AND gate along with the "=" output of the MSB comparator. When the MSB "=" is 0 (obvious inequality) the LSB outputs won't make it to the OR gates that sum the result. Otherwise, they will.

Here's a schematic of what I have in mind:

9. ### ol'trusty Thread Starter Member

Sep 9, 2009
48
0
Geo . It seems as though for input 00 11 we still receive equality...

10. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
What makes you say that? It looks fine to me. Do you see something I don't? I forgot to mention that the bit order goes A1A0 and B1B0, so the upper comparator compares the MSB's and the lower the LSB's.

Sep 9, 2009
48
0
Gotcha .

Thanks again