Hello,

I'm trying to design a 2 bit comperator unit using static cmos.

the unit function is [B+(AC)*(A+C)*]* (*->NOT)
where A,B are the input bits and C is the carry from the previous unit.

since the unit will be used as a base unit for a 8 bit comperator i must size the path to get the minimum dellay. My question is when do i use Skeweed High and when do I use Skeewed Low.
10x!

 

What kind of "comparator" is this?

Note that if B is HI, then the output is LO regardless of what A and C are. That doesn't sound like anything being compared to anything to me.

Try starting with a solid verbal description of what you want it to do and then prepare a Truth Table of what you think will meet those needs.

What what is "Skeewed High" and "Skeewed Low"?

 

system description: The system is a simple N bit comperator Fully Cmos. The system has 2N inputs and one output bit. The output bit is '1' only when A>B otherwise '0'.
For instance (N=4): A="0011" B="0010" -> Out='1'
A="0100" B="0100" -> Out='0'
A="0100" B="0110" -> Out='0'

The "UNIT" is a simple "one bit comperator" that will compare A B and C (the carry from the previous unit). Using N UNIT'S In series we get the Nbit comperator.

now, here is my Truth table

A B C OUT
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

and using Karno't table i got Out=[A*B+C*(A*B)]*

Now i need to do the transistor sizing so that the critical path (from C to out) dellay will be minimum.
And this is where i am stuck.

thanks alot

 

system description: The system is a simple N bit comperator Fully Cmos. The system has 2N inputs and one output bit. The output bit is '1' only when A>B otherwise '0'.

Thanks. That helps a lot. Note some of the discrepancies between this and you original description. First, you said that it was a 2-bit comparator while here it is described as a 1-bit comparator. Second, and the real key, is that the output function needed to be stated clearly, namely "the output bit is '1' only when A>B." There are five other possibilities.

For instance (N=4): A="0011" B="0010" -> Out='1'
A="0100" B="0100" -> Out='0'
A="0100" B="0110" -> Out='0'

The "UNIT" is a simple "one bit comperator" that will compare A B and C (the carry from the previous unit). Using N UNIT'S In series we get the Nbit comperator.

When you say "from the previous unit", I'm assuming you mean from the unit operating on the next least significant bit (i.e., from the circuit to the 'right'). At first glance, it is tempting to work from msb to lsb because as soon as you determine that A>B, you don't care what any of the lower order bits are. Can you see the problem with this approach?

now, here is my Truth table

A|B|C||OUT
0|0|0||0
0|0|1||1
0|1|0||0
0|1|1||0
1|0|0||1
1|0|1||1
1|1|0||0
1|1|1||1

This is correct. Note that I tweaked the formating of the table a bit.

Now, consider the power of a succinct verbal description of the logic:

If (A>B), then the output is HI regardless of the input, C, from the lower order bits.
If (A<B), then the output is LO regardless of the input, C, from the lower order bits.
If (A=B), then the output is equal to the input, C, from the lower order bits.

From this we can directly write the basic output equation:

Out = AB' + (AB + A'B')C
Out = AB' + ABC + A'B'C

and using Karno't table i got Out=[A*B+C*(A*B)]*

Originally you had " [B+(AC)*(A+C)*]* " and now you have " [A*B+C*(A*B)]* ".

Do either of these actually match the truth table?

Get in the habit of always asking if the answer makes sense.

Now i need to do the transistor sizing so that the critical path (from C to out) dellay will be minimum.
And this is where i am stuck.

Since you are now talking about transistor sizing, should we assume that you are talking about designing a transistor-level CMOS circuit? That wasn't at all obvious (to me) from the original post. Is it then also reasonable to assume that you are allowed to use direct implementation of the logic, as opposed to using standard gates? Is that what you meant by "fully CMOS"?

 

Quote:
When you say "from the previous unit", I'm assuming you mean from the unit operating on the next least significant bit (i.e., from the circuit to the 'right'). At first glance, it is tempting to work from msb to lsb because as soon as you determine that A>B, you don't care what any of the lower order bits are. Can you see the problem with this approach?


No, i must design one unit and then to use the same unit for N bits. So if you start From MSB to LSB not all units will necessarily work.

Quote:

now, here is my Truth table ABCOUT00000011010001101001101111001111

 

Quote:
When you say "from the previous unit", I'm assuming you mean from the unit operating on the next least significant bit (i.e., from the circuit to the 'right'). At first glance, it is tempting to work from msb to lsb because as soon as you determine that A>B, you don't care what any of the lower order bits are. Can you see the problem with this approach?


No, i must design one unit and then to use the same unit for N bits. So if you start From MSB to LSB not all units will necessarily work.

Quote:

now, here is my Truth table ...

How did you do that?

Quote:
Since you are now talking about transistor sizing, should we assume that you are talking about designing a transistor-level CMOS circuit? That wasn't at all obvious (to me) from the original post. Is it then also reasonable to assume that you are allowed to use direct implementation of the logic, as opposed to using standard gates? Is that what you meant by "fully CMOS"?

This is exactly the problem! I don't know.

I don't know when to use direct implementation of the logic and when to use standard gates.
If I use standard gates i need [B+(AC)*(A+C)*]* and i have 18 transistors per unit. But when i use direct implementation of the logic i can simplify the function and get [A*B+C*(A*B)]* which require only 14 transistors (i need 2 inverters for A' and C'). And as much as i understood from the lecture i should get the same resaults in both cases... So I am confused....

 

To separate columns using the table tags,

use the | separator.

Make sure that you have the same number of | on each line.

Tags must be enclosed in square braces, e.g. [newtag] and end with [/newtag]

 

No, i must design one unit and then to use the same unit for N bits. So if you start From MSB to LSB not all units will necessarily work.

But why won't they work? Understanding that is not critical to this problem, so put it on a back burner for now. But it is very educational and useful to develop the ability to not only understand, but to communicate things like this. For instance, what if a customer came to you to pay you to build this circuit and had in their mind that they way to do it was from msb to lsb (and it is not uncommon for customers to come to a designer thinking that they have the design all worked out and only need someone to implement it). How would you explain to them, or to a coworker, or to a junior engineer that you are mentoring, why it won't work? Again, it's not important to this problem, but do ponder it later.

I don't know when to use direct implementation of the logic and when to use standard gates.
If I use standard gates i need [B+(AC)*(A+C)*]* and i have 18 transistors per unit. But when i use direct implementation of the logic i can simplify the function and get [A*B+C*(A*B)]* which require only 14 transistors (i need 2 inverters for A' and C'). And as much as i understood from the lecture i should get the same resaults in both cases... So I am confused....

Before you can start talking about an implementation, you need a valid equation.

We already have the truth table for OUT, let's see what the truth tables are for the two expressions you have above:

X = [B+(AC)*(A+C)*]*
Y = [A*B+C*(A*B)]*

A|B|C||OUT||X|Y
0|0|0||0||0|1|
0|0|1||1||1|1|
0|1|0||0||0|0|
0|1|1||0||0|0|
1|0|0||1||1|1|
1|0|1||1||1|1|
1|1|0||0||0|1|
1|1|1||1||0|1|

Neither equation implements the desired logic!

In fact, you can simplify both X and Y equations quite a bit:

X = [B+(AC)*(A+C)*]*
X = [B+(A*+C*)(A*C*)]*
X = [B+(A*A*C*+C*A*C*)]*
X = [B+(A*C*+A*C*)]*
X = [B+A*C*]*
X = [B+(A+C)*]*

Since people don't think well in terms of NANDs and NORs, when checking things it is often useful to just run it to the basic operations with as few inversions on things other than single variables as you can:

X = [B+A*C*]*
X = (B*)(A*C*)*
X = B*(A+C)

From this, you can immediately see that X is HI only if B is LO (which is actually pretty evident from the original equation, too), but you know that you want Out to be HI when all three inputs are HI, thus X does NOT equal Out.

Now consider Y:

Y = [A*B+C*(A*B)]*
Y = [(A*B)+C*(A*B)]*
Y = [(A*B)(1+C*)]*
Y = [(A*B)]*
Y = (A*B)*
Y = A+B*

The input C has no effect at all, so you know this is wrong.

So work on getting a valid logic equation and then we will go from there.

As for when to use direct CMOS logic implementation, that is actually a question that touches on a lot of subjects, only a few of them purely EE. For the most part, direct implementation will usually result in the fastest and smallest solution, but is generally much more costly because of the design and layout time versus using standard cells, not to mention maintenance costs down the road as the design is updated and ported to newer processes or other designs. So you use it when the speed or size of a standard cell solution are not good enough.

 

OK, I got it .

Out= [A'B+C'(A'+B)]'

So the truth table is:

A|B|C||OUT
0|0|0||0
0|0|1||1
0|1|0||0
0|1|1||0
1|0|0||1
1|0|1||1
1|1|0||0
1|1|1||1

Now, I asked my instructor and he said that since this is a theoretical problem and since we won't be fabricating it, I should stick to the theory and have the fastest circuit as posible using as less area as posible.

10x

 

OK, I got it .

Out= [A'B+C'(A'+B)]'

Congrats! You were quite close, but my guess is that you just made a slight goof going from one line to the next. We all do it, which is why it's important to develop the tools and habits of always doing sanity checks to catch those things -- today not doing so loses you points on a piece of paper, tomorrow not doing so could cause a plane load of people to lose their lives. Always remember - doctors kill people one at a time, engineers kill in job lots.


So....

Q1) How many transistors would this require if the equation above were implemented directly using standard logic cells?

Q2) What would be the delay from each input to the output in terms of gate delays?

Q3) Which delay (i.e., which input to the output) is the one that really counts?

Q4) Could this be improved by massagine the equation? Hint: Which standard logic cells have only one gate delay? Can bubble logic (graphical application of DeMorgan's theorems) be used to maximize the use of such gates? Can the number of levels of logic be reduced by using multi-input (3 or more) logic gates?

Q4) Whats the best you can do with standard logic (transistors and gate delays)?

Now, I asked my instructor and he said that since this is a theoretical problem and since we won't be fabricating it, I should stick to the theory and have the fastest circuit as posible using as less area as posible.

This still leaves a lot of ground. For instance, NFETs are about twice "as fast" at room temperature as PFETs (that's a real sloppy statement, but basically the PFET in an inverter needs to have roughly twice the W/L as the NFET to get symmetric rise/fall times and drive strengths). Are you supposed to take this into account in any way (since it is very much fair game from a theoretical view point)? If not, then are you assuming that all of your transistors are the same size and have the same drive strength? Not realistic, but not an unreasonable simplification for a problem at this level, either.

What about the effect of series connected FETs? Are you supposed to take that effect into account?

In general, if you give me a circuit of a certain size and speed, I can probably make it faster by making it larger and, up to a point, make is smaller by letting it be slower (in a given process). So saying "fastest circuit possible while using the least area possible" is not a very good metric. If you must meet two goals that are in conflict, then your instructor really needs to give you some idea of what the value tradeoff between the two is.

Ponder all of this before we go on. We are actually making good headway.

 

Q1) How many transistors would this require if the equation above were implemented directly using standard logic cells?

5 for PUN +5 for PDN +4 for the two inverters =14 transistors tot.

Q2) What would be the delay from each input to the output in terms of gate delays?

In terms of gate delays (tg) we get :
For A and C 2tg (inverter).
For B 4tg (2 NMOS +2 PMOS).

Q3) Which delay (i.e., which input to the output) is the one that really counts?

From C to OUT since it is the last signal of all inputs to assume a stable value (critical path).

Q4) Could this be improved by massagine the equation? Hint: Which standard logic cells have only one gate delay? Can bubble logic (graphical application of DeMorgan's theorems) be used to maximize the use of such gates? Can the number of levels of logic be reduced by using multi-input (3 or more) logic gates?

Sorry i did not understand the question. Also, What do you mean by BUBBLE LOGIC?
As for reducing the number pf levels by using multi inputs logic gates, I think that it will only slow down the path. Since the delay of gates with hight fan in is grater (more serial logic to discharge/charge). So by reducing the number of levels (gaining area) we will slow the path down ( damaging performance).

Q4) Whats the best you can do with standard logic (transistors and gate delays)?

Using standart logic I could say that since the function is a Dual function (F(A,B,C)=F'(A',B',C')) the PUN is identical to the PDN. In that case i'll have only 2 serial transistors (worst case) instead of 3 in the PUN. ​

This still leaves a lot of ground. For instance, NFETs are about twice "as fast" at room temperature as PFETs (that's a real sloppy statement, but basically the PFET in an inverter needs to have roughly twice the W/L as the NFET to get symmetric rise/fall times and drive strengths). Are you supposed to take this into account in any way (since it is very much fair game from a theoretical view point)? If not, then are you assuming that all of your transistors are the same size and have the same drive strength? Not realistic, but not an unreasonable simplification for a problem at this level, either

I assume that due to the mobilty difference PMOS is "weaker" than the NMOS by the factor 'b' which I assume to be 2.18 for 35um technotogy we use in this corse. ​

What about the effect of series connected FETs? Are you supposed to take that effect into account?

If you nean charge sharing than the answer is YES. ​

In general, if you give me a circuit of a certain size and speed, I can probably make it faster by making it larger and, up to a point, make is smaller by letting it be slower (in a given process). So saying "fastest circuit possible while using the least area possible" is not a very good metric. If you must meet two goals that are in

As I understood the circuit should be as follows (by the order of importance)
1. Fast.
2. Minimum area.
3. Maximum Reliability.
4. Minimum Power.​

We are actually making good headway

Yey! ​